Patents by Inventor Satoshi Ogura
Satoshi Ogura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240150390Abstract: The purpose of the present invention is to provide a novel stereoselective method for preparing a cyclic dinucleotide derivative and a production intermediate therefor, which can be used for an antibody-immunostimulant conjugate. Also provided is a method for producing a cyclic dinucleotide-linker and an antibody-immunostimulant conjugate while using the above production method. Further provided is a method for preparing a cyclic dinucleotide derivative, the method including the step of subjecting a compound (I) and a compound (IV) to stereoselective condensation using an optically active phosphitylating agent (Rc-II) or (Sc-II).Type: ApplicationFiled: January 31, 2022Publication date: May 9, 2024Applicant: Daiichi Sankyo Company, LimitedInventors: Tomokazu OGURA, Takeshi NAKAYA, Hidekazu INOUE, Narumi ABE, Yuzo ABE, Tatsuya NAKAMURA, Yuko YAMAMOTO, Kohei SAKANISHI, Tatsuhiro SAKAMOTO, Satoshi NAKANE
-
Patent number: 11943414Abstract: An image processing apparatus includes a display device and a processor. The processor is configured to generate a first screen for display on the display device and on which one of a plurality of malfunctioning part candidates of the image processing apparatus and one of a plurality of timings at which a particular sound was output by the image processing apparatus that malfunctioned, are selectable, when a first malfunctioning part candidate and a first timing are selected on the first screen, generate a second screen for display on the display device and on which one or more reference sounds corresponding to the particular sound are selectable, and when one of the reference sounds is selected on the second screen, generate error information indicating the first malfunctioning part candidate and the selected reference sound.Type: GrantFiled: April 13, 2023Date of Patent: March 26, 2024Assignee: Toshiba Tec Kabushiki KaishaInventors: Sou Miyazaki, Hiroyo Tanaka, Kazuhiro Ogura, Masaki Narahashi, Satoshi Oyama, Tatsuya Inagi
-
Patent number: 11943398Abstract: A maintenance support system includes a network interface, a memory, and a processor configured to, upon receipt of first information indicating a status of a first apparatus via the network interface, store the first information in the memory, upon receipt of second information indicating a status of a second apparatus via the network interface, store the second information in the memory, and determine a priority of on-site maintenance between the first and second apparatuses based on the first and second information stored in the memory.Type: GrantFiled: April 27, 2023Date of Patent: March 26, 2024Assignee: Toshiba Tec Kabushiki KaishaInventors: Sou Miyazaki, Hiroyo Tanaka, Kazuhiro Ogura, Masaki Narahashi, Satoshi Oyama
-
Patent number: 11742595Abstract: The present invention performs characteristic tests on a communication device with a compact and simple configuration. A testing device 1 that performs characteristic tests in a near field on a communication antenna 250 of a communication device 240 includes a tray body 220 that supports the communication device in a test space S as an anechoic chamber, and a coupler support frame 520 that supports coupler antennas transmitting and receiving radio waves to/from the communication antenna 250. The coupler support frame can form inner-periphery coupler antenna arrays 300A and 300B each including a plurality of coupler antennas 300 arranged at least in a row along a curve extending along an inner peripheral surface composed of side surface S1 and S2, an upper surface S3, and a lower surface S4, and a rear coupler antenna array 300C including a plurality of coupler antennas 300 arranged at least in a row in an upper-lower direction along a curve extending along a rear surface S5.Type: GrantFiled: October 11, 2019Date of Patent: August 29, 2023Assignee: MORITA TECH CO., LTD.Inventors: Osamu Morita, Akinori Saeki, Kei Okamoto, Satoshi Ogura
-
Patent number: 11444383Abstract: An object of the present invention is to suppress occurrence of disturbance in pass amplitude characteristics within a band and disturbance in return loss characteristics in the band due to total reflection, improve cutoff performance, and acquire a favorable gain. An antenna device 1 includes a waveguide body 5 including a coaxial waveguide conversion unit 6 that includes an inner space 8 and a connector attachment hole 22, and a closure member 30. The antenna device 1 also includes a connector 50 including a connector body 51, a center conductor 60, and a radiator 54 b configured by an end portion 60 a of the center conductor that adapts the protruding length of the end portion to a specific frequency band.Type: GrantFiled: July 17, 2018Date of Patent: September 13, 2022Assignee: MORITA TECH CO., LTD.Inventors: Osamu Morita, Akinori Saeki, Satoshi Ogura
-
Patent number: 11417955Abstract: In the antenna device, a first insulating plate, a capacitive coupling portion of a tuning plate, a radio wave absorber, a grounding portion of the tuning plate folded back to the back side of the radio wave absorber, and a tuning coated plate provided with a metallic plated film formed on the surface thereof are sequentially stacked below an antenna element having a shape obtained by removing an arched portion from a copper circular plate. Power is supplied from a center conductor of a semi-rigid signal input member to a power feeding unit of the antenna element. An external conductor is held between the upper and lower conductive cushions. A grounding plate is conductive with the external conductor, to ground the grounding portion and the tuning coated plate.Type: GrantFiled: August 10, 2018Date of Patent: August 16, 2022Assignee: MORITA TECH CO., LTD.Inventors: Osamu Morita, Akinori Saeki, Kei Okamoto, Satoshi Ogura
-
Publication number: 20220013923Abstract: The present invention performs characteristic tests on a communication device with a compact and simple configuration. A testing device 1 that performs characteristic tests in a near field on a communication antenna 250 of a communication device 240 includes a tray body 220 that supports the communication device in a test space S as an anechoic chamber, and a coupler support frame 520 that supports coupler antennas transmitting and receiving radio waves to/from the communication antenna 250. The coupler support frame can form inner-periphery coupler antenna arrays 300A and 300B each including a plurality of coupler antennas 300 arranged at least in a row along a curve extending along an inner peripheral surface composed of side surface 51 and S2, an upper surface S3, and a lower surface S4, and a rear coupler antenna array 300C including a plurality of coupler antennas 300 arranged at least in a row in an upper-lower direction along a curve extending along a rear surface S5.Type: ApplicationFiled: October 11, 2019Publication date: January 13, 2022Applicant: MORITA TECH CO., LTD.Inventors: Osamu MORITA, Akinori SAEKI, Kei OKAMOTO, Satoshi OGURA
-
Publication number: 20210313690Abstract: By performing continuous matching in an entire frequency band from 600 MHz to 6 GHz by one antenna device, communication with a plurality of types of communication devices having different used frequency bands becomes possible without switching the antenna device. In the antenna device, a first insulating plate 40, a capacitive coupling portion 45a of a tuning plate 45, a radio wave absorber 50, a grounding portion 45b of the tuning plate 45 folded back to the back side of the radio wave absorber 50, and a tuning coated plate 55 provided with a metallic plated film formed on the surface thereof are sequentially stacked below an antenna element 30 having a shape obtained by removing an arched portion from a copper circular plate. Power is supplied from a center conductor 64 of a semi-rigid signal input member 61 to a power feeding unit 33 provided in a part of a circular outer edge 32 of the antenna element 30.Type: ApplicationFiled: August 10, 2018Publication date: October 7, 2021Applicant: MORITA TECH CO., LTD.Inventors: Osamu MORITA, Akinori SAEKI, Kei OKAMOTO, Satoshi OGURA
-
Publication number: 20200335872Abstract: An object of the present invention is to suppress occurrence of disturbance in pass amplitude characteristics within a band and disturbance in return loss characteristics in the band due to total reflection, improve cutoff performance, and acquire a favorable gain. An antenna device 1 includes a waveguide body 5 including a coaxial waveguide conversion unit 6 that is hexahedral and includes an inner space 8 formed by penetrating a first surface and a second surface facing each other and a connector attachment hole 22 for inserting a coaxial connector continuously formed between a third surface orthogonal to the first surface and the second surface and the inner space, and a closure member 30 that is conductive and closes an opening of the inner space on the second surface side.Type: ApplicationFiled: July 17, 2018Publication date: October 22, 2020Applicant: MORITA TECH CO., LTD.Inventors: Osamu MORITA, Akinori SAEKI, Satoshi OGURA
-
Publication number: 20110138152Abstract: A processor which executes threads having different characteristics is provided with an instruction control device. In the instruction control device, a first instruction control unit issues an instruction included in a first instruction sequence to an instruction execution unit. In addition, a second instruction control unit issues an instruction included in a second instruction sequence to the instruction execution unit. Here, the delay time of the second instruction control unit is shorter than the delay time of the first instruction control unit.Type: ApplicationFiled: August 18, 2009Publication date: June 9, 2011Applicant: PANASONIC CORPORATIONInventor: Satoshi Ogura
-
Patent number: 7822949Abstract: A command supply device supplies a command sequence that forms a loop. A loop command buffer accumulates a first partial command sequence. The first partial command sequence is a head part of a first command sequence repeatedly supplied to a CPU from among command sequences stored in a main memory, and is accumulated before the first command sequence is supplied to the CPU again. A linking command buffer accumulates a second partial command sequence. The second partial command sequence follows the first partial command sequence in the first command sequence, and is accumulated while the accumulated first partial command sequence in the loop command buffer is supplied to the CPU. A selection circuit supplies, to the CPU, a command from the accumulated second partial command sequence in the linking command buffer when the entirety of the first partial command sequence has been supplied to the CPU.Type: GrantFiled: May 9, 2005Date of Patent: October 26, 2010Assignee: Panasonic CorporationInventor: Satoshi Ogura
-
Publication number: 20080086621Abstract: A command supply device is provided that efficiently supplies a command sequence that forms a loop. The command supply device includes a loop command buffer in which the command supply device accumulates a first partial command sequence that is a head part of a first command sequence repeatedly supplied to the central processing unit from among command sequences stored in a main memory, before supplying the first command sequence to the central processing unit again.Type: ApplicationFiled: May 9, 2005Publication date: April 10, 2008Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Satoshi Ogura
-
Patent number: 6320321Abstract: In order to uniformly neutralize a large current and a large diameter ion beam so as to irradiate an ion beam having a reduced beam divergence on a process target, an ion beam processing apparatus comprises an ion source for producing a processing plasma, a processing chamber as a vacuum chamber for accommodating a process target, an extract electrode for extracting an ion beam so as to irradiate on said process target, an annular electrode disposed in said processing chamber for forming an annular magnetic field therein, through which said ion beam is irradiated on said process, and a wave guide for introducing microwave through an opening provided on a wall forming said processing chamber, into said annular magnetic field.Type: GrantFiled: January 2, 2001Date of Patent: November 20, 2001Assignee: Hitachi, Ltd.Inventors: Satoshi Ogura, Shotaro Ooishi, Isao Hashimoto, Satoshi Ichimura
-
Publication number: 20010005119Abstract: In order to uniformly neutralize a large current and a large diameter ion beam so as to irradiate an ion beam having a reduced beam divergence on a process target, an ion beam processing apparatus comprises an ion source for producing a processing plasma, a processing chamber as a vacuum chamber for accommodating a process target, an extract electrode for extracting an ion beam so as to irradiate on said process target, an annular electrode disposed in said processing chamber for forming an annular magnetic field therein, through which said ion beam is irradiated on said process, and a wave guide for introducing microwave through an opening provided on a wall forming said processing chamber, into said annular magnetic field.Type: ApplicationFiled: January 2, 2001Publication date: June 28, 2001Applicant: Hitachi, Ltd.Inventors: Satoshi Ogura, Shotaro Ooishi, Isao Hashimoto, Satashi Ichimura
-
Patent number: 6189092Abstract: A processor executes a program loop at high speed using a branch target information register instruction which is set immediately before the program loop and a high-speed loop instruction which is set at an end of the program loop. When the branch target information register instruction is decoded by an instruction decoder, code in a fetched instruction buffer is sent to a branch target instruction register, and a shifted pointer in a decoded instruction counter is sent to a branch target fetch address register. After the high-speed loop instruction has been decoded by the instruction decoder and a branch condition is satisfied, the pointer in the branch target fetch address register is sent to a fetched instruction counter and to the decoded instruction counter while the code in the branch target instruction register is sent to a decoded instruction buffer. By using the shifted pointer in the decoded instruction counter, the high-speed loop instruction can be efficiently executed with small-scale hardware.Type: GrantFiled: June 18, 1998Date of Patent: February 13, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Satoshi Ogura, Shinji Ozaki
-
Patent number: 6184625Abstract: In order to uniformly neutralize a large current and a large diameter ion beam so as to irradiate an ion beam having a reduced beam divergence on a process target, an ion beam processing apparatus comprises an ion source for producing a processing plasma, a processing chamber as a vacuum chamber for accommodating a process target, an extract electrode for extracting an ion beam so as to irradiate on said process target, an annular electrode disposed in said processing chamber for forming an annular magnetic field therein, through which said ion beam is irradiated on said process, and a wave guide for introducing microwave through an opening provided on a wall forming said processing chamber, into said annular magnetic field.Type: GrantFiled: June 8, 1999Date of Patent: February 6, 2001Assignee: Hitachi, Ltd.Inventors: Satoshi Ogura, Shotaro Ooishi, Isao Hashimoto, Satoshi Ichimura
-
Patent number: 6161171Abstract: A first instruction requiring that a data word should be read out from a data memory and be stored in a certain register in a register set, and then a second instruction requiring that two operands, respectively read out from the register and another register in the register set, should be added are pipeline-processed. In a high-speed mode in which an operation clock having a higher frequency is supplied, a data cache intervened between an instruction execution circuit and the data memory is controlled to supply a data word to a WB (write back) stage of the instruction execution circuit within two cycles with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is supplied from the WB stage to an EX (operation execution) stage of the instruction execution circuit.Type: GrantFiled: June 26, 1998Date of Patent: December 12, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toru Morikawa, Nobuo Higaki, Shinji Ozaki, Keisuke Kaneko, Satoshi Ogura, Masato Suzuki
-
Patent number: 5847978Abstract: A processor including an arithmetic operation circuit and a saturation operation correction circuit both of which are connected in parallel to a register and a data bus and are activated by respective operation instructions. The saturation operation correction circuit judges whether an output from a register file exceeds either of a predetermined upper-most value and a predetermined lower-most value, and selectively outputs one of an operation result, the upper-most value, and the lower-most value.Type: GrantFiled: September 27, 1996Date of Patent: December 8, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Satoshi Ogura, Shinya Miyaji, Nobuo Higaki, Masato Suzuki
-
Patent number: 5835505Abstract: A semiconductor integrated circuit includes a functional block realizing at least part of a function of the semiconductor integrated circuit. The functional block includes a plurality of basic cells and a plurality of terminal cells. Each of the plurality of terminal cells has a connector for mediating a communication between another semiconductor integrated circuit and one of the plurality of basic cells.Type: GrantFiled: April 16, 1997Date of Patent: November 10, 1998Assignee: Matsushita Electric Industrial Co., ltd.Inventors: Yoshito Nishimichi, Satoshi Ogura, Shinji Ozaki, Seiji Tokunoh, Akira Miyoshi, Hiroaki Yamamoto, Yoshiaki Kasuga
-
Patent number: 5815038Abstract: A small-sized distortion compensation circuit is disclosed. In a semi-conductor element having three terminals, its gate is used as an input terminal. One of the drain and source is used as an output terminal, and the other is grounded. This structure does not need a conventionally used circuit comprising a complicated combination of distributors, couplers and attenuators, enabling the circuit to be smaller.Type: GrantFiled: April 22, 1996Date of Patent: September 29, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Satoshi Ogura, Kiyoharu Seino, Tomohiko Ono, Akihiro Kamikokura, Haruzo Hirose