Patents by Inventor Satoshi Oka

Satoshi Oka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240112211
    Abstract: A data price determination apparatus includes acquires yield prediction data of a production target in agriculture, acquires a reference price, which is a reference sales price of the yield prediction data, acquires a sales price coefficient based on temporal variation of the yield prediction data, and corrects the reference price using the sales price coefficient and calculates a sales price of the yield prediction data.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 4, 2024
    Inventors: RYUYA OKA, SATOSHI IGETA
  • Patent number: 8823130
    Abstract: A silicon epitaxial wafer having a silicon epitaxial layer grown by vapor phase epitaxy on a main surface of a silicon single crystal substrate, wherein the main surface of the silicon single crystal substrate is tilted with respect to a [100] axis at an angle ? in a [011] direction or a [0-1-1] direction from a (100) plane and at an angle ? in a [01-1] direction or a [0-11] direction from the (100) plane, the angle ? and the angle ? are less than ten minutes, and a dopant concentration of the silicon epitaxial layer is equal to or more than 1×1019/cm3. Even when an epitaxial layer having a dopant concentration of 1×1019/cm3 or more is formed on the main surface of the silicon single crystal substrate, stripe-shaped surface irregularities on the epitaxial layer are inhibited.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: September 2, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masahiro Kato, Satoshi Oka, Norihiro Kobayashi, Tohru Ishizuka, Nobuhiko Noto
  • Patent number: 8728912
    Abstract: The present invention is directed to a method for manufacturing an SOI wafer, the method by which treatment that removes the outer periphery of a buried oxide film to obtain a structure in which a peripheral end of an SOI layer of an SOI wafer is located outside a peripheral end of the buried oxide film, and, after heat treatment is performed on the SOI wafer in a reducing atmosphere containing hydrogen or an atmosphere containing hydrogen chloride gas, an epitaxial layer is formed on a surface of the SOI layer. As a result, there is provided a method that can manufacture an SOI wafer having a desired SOI layer thickness by performing epitaxial growth without allowing a valley-shaped step to be generated in an SOI wafer with no silicon oxide film in a terrace portion, the SOI wafer fabricated by an ion implantation delamination method.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: May 20, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroji Aga, Isao Yokokawa, Satoshi Oka
  • Patent number: 8691665
    Abstract: The present invention is directed to a method for producing a bonded wafer, the method in which heat treatment for flattening the surface of a thin film is performed on a bonded wafer made by the ion implantation delamination method in an atmosphere containing hydrogen or hydrogen chloride, wherein the surface of a susceptor on which the bonded wafer is to be placed, the susceptor used at the time of flattening heat treatment, is coated with a silicon film in advance. As a result, a method for producing a bonded wafer is provided, the method by which a bonded wafer having a thin film with good film thickness uniformity can be obtained even when heat treatment for flattening the surface of a thin film of a bonded wafer after delamination is performed in the ion implantation delamination method.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: April 8, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Satoshi Oka, Hiroji Aga, Masahiro Kato, Nobuhiko Noto
  • Publication number: 20130316522
    Abstract: The present invention is directed to a method for manufacturing an SOI wafer, the method by which treatment that removes the outer periphery of a buried oxide film to obtain a structure in which a peripheral end of an SOI layer of an SOI wafer is located outside a peripheral end of the buried oxide film, and, after heat treatment is performed on the SOI wafer in a reducing atmosphere containing hydrogen or an atmosphere containing hydrogen chloride gas, an epitaxial layer is formed on a surface of the SOI layer. As a result, there is provided a method that can manufacture an SOI wafer having a desired SOI layer thickness by performing epitaxial growth without allowing a valley-shaped step to be generated in an SOI wafer with no silicon oxide film in a terrace portion, the SOI wafer fabricated by an ion implantation delamination method.
    Type: Application
    Filed: November 18, 2011
    Publication date: November 28, 2013
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroji Aga, Isao Yokokawa, Satoshi Oka
  • Patent number: 8497187
    Abstract: According to the present invention, there is provided a method for manufacturing an SOI wafer, the method configured to grow an epitaxial layer on an SOI layer of the SOI wafer having the SOI layer on a BOX layer to increase a thickness of the SOI layer, wherein epitaxial growth is carried out by using an SOI wafer whose infrared reflectance in an infrared wavelength range of 800 to 1300 nm falls within the range of 20% to 40% as the SOI wafer on which the epitaxial layer is grown. As a result, a high-quality SOI wafer with less slip dislocation and others can be provided with excellent productivity at a low cost as the SOI wafer including the SOI layer having a thickness increased by growing the epitaxial layer, and a manufacturing method thereof can be also provide.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: July 30, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Satoshi Oka, Susumu Kuwabara
  • Publication number: 20130102126
    Abstract: A method for manufacturing a bonded wafer including: forming an ion-implanted layer in a bond wafer, bonding the bond wafer to a base wafer, delaminating the bond wafer at the ion-implanted layer, and performing a flattening heat treatment on a surface after delamination, in which a silicon single crystal wafer is used as the bond wafer where the region to form the ion-implanted layer has a resistivity of 0.2 ?cm or less, the ion-implanted layer is formed where the ion dose for forming the layer is 4×1016/cm2 or less, and the flattening heat treatment is performed in an atmosphere including HCl gas. Therefore, a method for manufacturing a bonded wafer having a low resistivity thin film (SOI layer) that contains dopant, such as boron, with high concentration according to the ion-implantation delamination method, where outward diffusion of dopant and suction due to oxidation can be inhibited to maintain low resistivity.
    Type: Application
    Filed: April 21, 2011
    Publication date: April 25, 2013
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroji Aga, Satoshi Oka, Nobuhiko Noto
  • Patent number: 8389382
    Abstract: A method for manufacturing a bonded wafer including the steps of: implanting at least one gas ion of a hydrogen ion and a rare gas ion into a bond wafer from a surface thereof to form an ion-implanted layer; bonding the ion-implanted surface of the bond wafer to a surface of a base wafer directly or through an oxide film; thereafter delaminating the bond wafer at the ion-implanted layer to prepare the bonded wafer having a silicon thin film formed on the base wafer; and performing a flattening heat treatment on the bonded wafer under an atmosphere containing hydrogen or hydrogen chloride, wherein a dopant gas is added into the atmosphere of the flattening heat treatment to perform the heat treatment, the dopant gas having the same conductivity type as a dopant contained in the silicon thin film.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: March 5, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Satoshi Oka, Nobuhiko Noto
  • Publication number: 20120326268
    Abstract: A silicon epitaxial wafer having a silicon epitaxial layer grown by vapor phase epitaxy on a main surface of a silicon single crystal substrate, wherein the main surface of the silicon single crystal substrate is tilted with respect to a [100] axis at an angle ? in a [011] direction or a [0-1-1] direction from a (100) plane and at an angle ? in a [01-1] direction or a [0-11] direction from the (100) plane, the angle ? and the angle ? are less than ten minutes, and a dopant concentration of the silicon epitaxial layer is equal to or more than 1×1019/cm3. Even when an epitaxial layer having a dopant concentration of 1×1019/cm3 or more is formed on the main surface of the silicon single crystal substrate, stripe-shaped surface irregularities on the epitaxial layer are inhibited.
    Type: Application
    Filed: March 1, 2011
    Publication date: December 27, 2012
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Masahiro Kato, Satoshi Oka, Norihiro Kobayashi, Tohru Ishizuka, Nobuhiko Noto
  • Publication number: 20120244679
    Abstract: The present invention is directed to a method for producing a bonded wafer, the method in which heat treatment for flattening the surface of a thin film is performed on a bonded wafer made by the ion implantation delamination method in an atmosphere containing hydrogen or hydrogen chloride, wherein the surface of a susceptor on which the bonded wafer is to be placed, the susceptor used at the time of flattening heat treatment, is coated with a silicon film in advance. As a result, a method for producing a bonded wafer is provided, the method by which a bonded wafer having a thin film with good film thickness uniformity can be obtained even when heat treatment for flattening the surface of a thin film of a bonded wafer after delamination is performed in the ion implantation delamination method.
    Type: Application
    Filed: November 18, 2010
    Publication date: September 27, 2012
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Satoshi Oka, Hiroji Aga, Masahiro Kato, Nobuhiko Noto
  • Patent number: 8076223
    Abstract: The present invention is a method for producing a semiconductor substrate, including steps of forming a SiGe gradient composition layer and a SiGe constant composition layer on a Si single crystal substrate, flattening a surface of the SiGe constant composition layer, removing a natural oxide film on the flattened surface of the SiGe constant composition layer, and forming a strained Si layer on the surface of the SiGe constant composition layer from which the natural oxide film has been removed, wherein the formation of the SiGe gradient composition layer and the formation of the SiGe constant composition layer are performed at a temperature T1 that is higher than 800° C., the removal of the natural oxide film from the surface of the SiGe constant composition layer is performed in a reducing atmosphere through a heat treatment at a temperature T2 that is equal to or higher than 800° C.
    Type: Grant
    Filed: July 4, 2007
    Date of Patent: December 13, 2011
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Satoshi Oka, Nobuhiko Noto
  • Publication number: 20110237049
    Abstract: A method for manufacturing a bonded wafer including the steps of: implanting at least one gas ion of a hydrogen ion and a rare gas ion into a bond wafer from a surface thereof to form an ion-implanted layer; bonding the ion-implanted surface of the bond wafer to a surface of a base wafer directly or through an oxide film; thereafter delaminating the bond wafer at the ion-implanted layer to prepare the bonded wafer having a silicon thin film formed on the base wafer; and performing a flattening heat treatment on the bonded wafer under an atmosphere containing hydrogen or hydrogen chloride, wherein a dopant gas is added into the atmosphere of the flattening heat treatment to perform the heat treatment, the dopant gas having the same conductivity type as a dopant contained in the silicon thin film.
    Type: Application
    Filed: October 15, 2009
    Publication date: September 29, 2011
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Satoshi Oka, Nobuhiko Noto
  • Publication number: 20110117727
    Abstract: According to the present invention, there is provided a method for manufacturing an SOI wafer, the method configured to grow an epitaxial layer on an SOI layer of the SOI wafer having the SOI layer on a BOX layer to increase a thickness of the SOI layer, wherein epitaxial growth is carried out by using an SOI wafer whose infrared reflectance in an infrared wavelength range of 800 to 1300 nm falls within the range of 20% to 40% as the SOI wafer on which the epitaxial layer is grown. As a result, a high-quality SOI wafer with less slip dislocation and others can be provided with excellent productivity at a low cost as the SOI wafer including the SOI layer having a thickness increased by growing the epitaxial layer, and a manufacturing method thereof can be also provide.
    Type: Application
    Filed: July 29, 2009
    Publication date: May 19, 2011
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Satoshi Oka, Susumu Kuwabara
  • Patent number: 7838388
    Abstract: Provided is a method for producing an SOI substrate having a thick-film SOI layer, in which an ion-implanted layer is formed by implanting at least one kind of ion of hydrogen ion and a rare gas ion into a surface of a bond wafer, an SOI substrate having an SOI layer is produced by, after the ion-implanted surface of the bond wafer and a surface of a base wafer are bonded together via an oxide film, delaminating the bond wafer along the ion-implanted layer, heat treatment is performed on the SOI substrate having the SOI layer in a reducing atmosphere containing hydrogen or an atmosphere containing hydrogen chloride gas, and, after the surface of the SOI layer is polished by CMP, a silicon epitaxial layer is grown on the SOI layer of the SOI substrate.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: November 23, 2010
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Satoshi Oka, Nobuhiko Noto
  • Publication number: 20100003803
    Abstract: According to the present invention, there is provided a manufacturing method of a strained Si substrate including at least steps of: forming a lattice-relaxed SiGe layer on a silicon single crystal substrate; flattening a surface of the SiGe layer by CMP; and forming a strained Si layer on the surface of the flattened SiGe layer, wherein the method comprises steps of: subjecting the surface of the SiGe layer to SC1 cleaning, before forming the strained Si layer on the lattice-relaxed SiGe layer surface that is flattened; heat-treating the substrate having the SiGe layer after being subjected to SC1 cleaning in a hydrogen-containing atmosphere at 800° C. or higher; immediately forming a protective Si layer on the SiGe layer surface on the heat-treated substrate, without lowering the temperature below 800° C. after the heat treatment; and forming the strained Si layer on the surface of the protective Si layer at a temperature lower than the temperature of forming the protective Si layer.
    Type: Application
    Filed: November 29, 2007
    Publication date: January 7, 2010
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Satoshi Oka, Nobuhiko Noto
  • Publication number: 20090305485
    Abstract: The present invention is a method for producing a semiconductor substrate, including steps of forming a SiGe gradient composition layer and a SiGe constant composition layer on a Si single crystal substrate, flattening a surface of the SiGe constant composition layer, removing a natural oxide film on the flattened surface of the SiGe constant composition layer, and forming a strained Si layer on the surface of the SiGe constant composition layer from which the natural oxide film has been removed, wherein the formation of the SiGe gradient composition layer and the formation of the SiGe constant composition layer are performed at a temperature T1 that is higher than 800° C., the removal of the natural oxide film from the surface of the SiGe constant composition layer is performed in a reducing atmosphere through a heat treatment at a temperature T2 that is equal to or higher than 800° C.
    Type: Application
    Filed: July 4, 2007
    Publication date: December 10, 2009
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventors: Satoshi Oka, Nobuhiko Noto
  • Publication number: 20090258474
    Abstract: Provided is a method for producing an SOI substrate having a thick-film SOI layer, in which an ion-implanted layer is formed by implanting at least one kind of ion of hydrogen ion and a rare gas ion into a surface of a bond wafer, an SOI substrate having an SOI layer is produced by, after the ion-implanted surface of the bond wafer and a surface of a base wafer are bonded together via an oxide film, delaminating the bond wafer along the ion-implanted layer, heat treatment is performed on the SOI substrate having the SOI layer in a reducing atmosphere containing hydrogen or an atmosphere containing hydrogen chloride gas, and, after the surface of the SOI layer is polished by CMP, a silicon epitaxial layer is grown on the SOI layer of the SOI substrate.
    Type: Application
    Filed: March 4, 2009
    Publication date: October 15, 2009
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Satoshi Oka, Nobuhiko Noto
  • Patent number: 7029977
    Abstract: A fabrication method of a semiconductor wafer can fill trenches formed in a semiconductor substrate with an epitaxial film with high crystal quality without leaving cavities in the trenches. The trenches are formed in the first conductivity type semiconductor substrate. Planes exposed inside the trenches are made clean surfaces by placing the substrate in a gas furnace, followed by supplying the furnace with an etching gas and carrier gas, and by performing etching on the exposed planes inside the trenches by a thickness from about a few nanometers to one micrometer. The trenches have a geometry opening upward through the etching. Following the etching, a second conductivity type semiconductor is epitaxially grown in the trenches by supplying the furnace with a growth gas, etching gas, doping gas and carrier gas, thereby filling the trenches. Instead of making the trenches slightly-opened upward, their sidewalls may be made planes enabling facet formation.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: April 18, 2006
    Assignees: Fuji Electric Holdings Co., Ltd., Shin-Etsu Handotai Co., Ltd.
    Inventors: Daisuke Kishimoto, Susumu Iwamoto, Katsunori Ueno, Ryohsuke Shimizu, Satoshi Oka
  • Patent number: 7008881
    Abstract: A silicon epitaxial layer is formed on the semiconductor underlayer of a target substrate (W) in the process chamber (2). This forming method includes a pressure reducing step of reducing the pressure inside the process chamber (2) accommodating the target substrate (W), a vapor phase growth step of introducing a film formation gas containing silane gas into the process chamber (2) to grow a silicon epitaxial layer on the semiconductor underlayer, and a hydrogen chloride treatment step and a hydrogen heat treatment step performed therebetween. The hydrogen chloride treatment step is arranged to introduce the first pre-treatment gas containing hydrogen chloride gas into the process chamber (2), thereby treating the atmosphere inside the process chamber (2). The hydrogen heat treatment step is arranged to introduce the second pre-treatment gas containing hydrogen gas into the process chamber (2), thereby treating the surface of the semiconductor underlayer.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: March 7, 2006
    Assignee: Tokyo Electron Limited
    Inventors: Akitake Tamura, Satoshi Oka
  • Publication number: 20040185665
    Abstract: A fabrication method of a semiconductor wafer can fill trenches formed in a semiconductor substrate with an epitaxial film with high crystal quality without leaving cavities in the trenches. The trenches are formed in the first conductivity type semiconductor substrate. Planes exposed inside the trenches are made clean surfaces by placing the substrate in a gas furnace, followed by supplying the furnace with an etching gas and carrier gas, and by performing etching on the exposed planes inside the trenches by a thickness from about a few nanometers to one micrometer. The trenches have a geometry opening upward through the etching. Following the etching, a second conductivity type semiconductor is epitaxially grown in the trenches by supplying the furnace with a growth gas, etching gas, doping gas and carrier gas, thereby filling the trenches. Instead of making the trenches slightly-opened upward, their sidewalls may be made planes enabling facet formation.
    Type: Application
    Filed: March 5, 2004
    Publication date: September 23, 2004
    Applicants: FUJI ELECTRIC HOLDINGS CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Daisuke Kishimoto, Susumu Iwamoto, Katsunori Ueno, Ryosuke Shimizu, Satoshi Oka