Abstract: A radar apparatus includes a first radar apparatus that transmits and receives a signal with a first frequency and has a first detection area, and a second radar apparatus that transmits and receives a signal with a second frequency different from the first frequency and has a second detection area different from the first detection area. The first radar apparatus and the second radar apparatus are arranged on a vehicle such that the first detection area and the second detection area partially overlap with each other. The second radar apparatus generates second information. The first radar apparatus generates first information, performs arithmetic integration processing based on the first information and the second information to generate integrated information, and transmits the integrated information to a higher-level apparatus.

Abstract: A frame interpolation apparatus receives moving images from an image generating apparatus that outputs moving images by increasing the number of frames by adding n units (n being a natural number) of copy frame following each frame of the moving images. A frame acquisition unit samples a frame from the moving images in cycles of (n+1) frames. An interpolated frame generation unit generates an interpolated frame to be inserted between the frames sampled by the frame acquisition unit. An identity determining unit determines the identity of successive frames of the moving images. A sampling point changing unit shifts a sampling point while keeping fixed cycles when there is a succession of less than or more than (n+1) frames determined to be identical by the identity determining unit and besides a certain condition is met.

Abstract: An input unit writes, into a memory unit, frames successively input from the outside. An interpolated frame generating unit reads multiple original frames from the memory unit, generates an interpolated frame between the original frames, and writes the interpolated frame into the memory unit. An output unit retrieves original frames and an interpolated frame from the memory unit and outputs to the outside the frames in the order in which the frames are to be displayed. The input unit, interpolated frame generating unit, and output unit operate in parallel to perform pipeline processing. Operation timing of each of the input unit and the interpolated frame generating unit is determined so that the timing at which the input unit writes an original frame into the memory unit differs from the timing at which the interpolated frame generating unit writes an interpolated frame into the memory unit.

Abstract: A frame interpolation apparatus receives moving images from an image generating apparatus that outputs moving images by increasing the number of frames by adding n units (n being a natural number) of copy frame following each frame of the moving images. A frame acquisition unit samples a frame from the moving images in cycles of (n+1) frames. An interpolated frame generation unit generates an interpolated frame to be inserted between the frames sampled by the frame acquisition unit. An identity determining unit determines the identity of successive frames of the moving images. A sampling point changing unit shifts a sampling point while keeping fixed cycles when there is a succession of less than or more than (n+1) frames determined to be identical by the identity determining unit and besides a certain condition is met.

Abstract: A signal processing circuit detects a pulsative change point of an input signal and sets a phase point which is shifted by a predetermined phase difference from the detected pulsative change point of the input signal as the timing for sampling the input signal.

Abstract: An input unit writes, into a memory unit, frames successively input from the outside. An interpolated frame generating unit reads multiple original frames from the memory unit, generates an interpolated frame between the original frames, and writes the interpolated frame into the memory unit. An output unit retrieves original frames and an interpolated frame from the memory unit and outputs to the outside the frames in the order in which the frames are to be displayed. The input unit, interpolated frame generating unit, and output unit operate in parallel to perform pipeline processing. Operation timing of each of the input unit and the interpolated frame generating unit is determined so that the timing at which the input unit writes an original frame into the memory unit differs from the timing at which the interpolated frame generating unit writes an interpolated frame into the memory unit.

Abstract: A signal processing circuit detects a pulsative change point of an input signal and sets a phase point which is shifted by a predetermined phase difference from the detected pulsative change point of the input signal as the timing for sampling the input signal.