Abstract: An ATM signal generator generates packet signals by linking N data blocks that includes user data and a specifier byte containing a sequence number bit. A transmitter receives the packet signals, generates control signals containing length information, generates N−1 ATM cells accommodating one data block in the payload, generates one ATM cell accommodating one data block and a control signal in the payload, and transmits all of the ATM cells to a communications path. A receiver receives ATM cells from the communications path, detects the number of cell rejections using the sequence number bits extracted from the specifier bytes in all of the ATM cells, and detects the number of bit error occurrences using the length information extracted from the control signals.

Abstract: A jitter resistant clock regenerator for receiving program data transmitted on a transmission channel in synchronism with a transmission clock signal and cancelling jitter, having occurred on the channel, to restore from the transmitted program data a highly accurate program clock signal from which the jitter is removed. The regenerator includes a buffer for temporarily storing transmitted data received over the channel. A read clock selector monitors the buffer to determine the amount of the transmitted data stored in the buffer, and selects one of read clock signals in response to the data amount. A program clock acquisition circuit reads out the transmitted data from the buffer in response to a read clock signal selected by the selector, and restores the clock signal of the program data from the transmitted data.

Abstract: A parity check circuit for inspecting a piece of binary information having n bits including a parity bit provided with n EXCLUSIVE-OR circuits for receiving each bit of the piece of binary information, at least one stage composed of EXCLUSIVE-OR circuits having the number of a half of the previous stage until the number of the EXCLUSIVE-OR circuits reaches one, and an error detector, further including at least one data register circuit intervening between each of the stages and for receiving a set of data from the previous stage, forwarding the previous set of data which has been registered therein toward the next stage, and registering the set of data newly delivered to the stage, in response to a check signal.

Abstract: A ferritic stainless steel exhibiting excellent atmospheric corrosion resistance and crevice corrosion resistance can be provided by positively adding P thereto and by adequately adjusting Ca and Al. The ferritic stainless steel according to the present invention essentially consists of, in weight percentages,C: about 0.05% or lessSi: about 1.0% or lessCr: about 11% or more and less than about 20%Mn: about 1.0% or lessN: about 0.10% or lessS: about 0.03% or lessCa: about 5 ppm or more and about 50 ppm or lessAl: about 0.5% or lessP: more than about 0.04% and about 0.20% or lessand the balance being iron and incidental impurities. The stainless steel according to the present invention may also contain at least one element selected from a group (1) consisting of about 6% or less of Mo, group (2) consisting of about 1.0% or less of Cu, about 3% or less of Ni and about 3% or less of Co, or group (3) consisting of about 1.0% or less of Ti, about 1.0% or less of Nb, about 1.0% or less of V, about 1.