Patents by Inventor Satoshi Rittaku
Satoshi Rittaku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9865513Abstract: A semiconductor device manufacturing method includes an element forming step of forming an element structure on a front surface of a substrate and forming a back structure on a back surface of the substrate, and a film forming step of performing film forming on a front surface of the element structure while measuring the temperature of the substrate by using a radiation thermometer that applies infrared rays of a wavelength ?i to the back structure to obtain an infrared emissivity of the substrate. The back structure has a first layer exposed to the outside and a second layer in contact with the first layer, the refractive index of the second layer being smaller than that of the first layer, and the layer thickness of the first layer is set in a range from (2n?1)?i/8 to (2n+1)?i/8, with n being a positive even number.Type: GrantFiled: May 21, 2014Date of Patent: January 9, 2018Assignee: Mitsubishi Electric CorporationInventors: Takuichiro Shitomi, Kazuhisa Koga, Satoshi Rittaku
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Publication number: 20170040229Abstract: A semiconductor device manufacturing method includes an element forming step of forming an clement structure on a front surface of a substrate and forming a back structure on a back surface of the substrate, and a film forming step of performing film forming on a front surface of the element structure while measuring the temperature of the substrate by using a radiation thermometer that applies infrared rays of a wavelength ?i to the back structure to obtain an infrared emissivity of the substrate. The back structure has a first layer exposed to the outside and a second layer in contact with the first layer, the refractive index of the second layer being smaller than that of the first layer, and the layer thickness of the first layer is set in a range from (2n?1)?i/8 to (2n+1)?i/8, with n being a positive even number.Type: ApplicationFiled: May 21, 2014Publication date: February 9, 2017Applicant: Mitsubishi Electric CorporationInventors: Takuichiro SHITOMI, Kazuhisa KOGA, Satoshi RITTAKU
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Patent number: 8044487Abstract: A semiconductor device including a high voltage element and a low voltage element, including: a semiconductor substrate having high voltage element region where the high voltage element is formed, and a low voltage element region where the low voltage element is formed; a first LOCOS isolation structure disposed in the high voltage element region; and a second LOCOS isolation structure disposed in the low voltage element region, wherein the first LOCOS isolation structure includes a LOCOS oxide film formed on a surface of the semiconductor substrate and a CVD oxide film formed on the LOCOS oxide film, and the second LOCOS isolation structure includes a LOCOS oxide film.Type: GrantFiled: December 15, 2006Date of Patent: October 25, 2011Assignee: Mitsubishi Electric CorporationInventors: Satoshi Rittaku, Kazuhiro Shimizu
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Publication number: 20110212594Abstract: An n-type buried diffusion layer is formed on the surface layer of the prescribed area of a p-type silicon substrate, and a p-type first high-concentration isolation diffusion layer is formed in the silicon substrate so as to surround the buried diffusion layer. An n-type epitaxial layer is formed on the silicon substrate, the buried diffusion layer, and the first high-concentration isolation diffusion layer. A p-type second high-concentration isolation diffusion layer is formed in the epitaxial layer on the first high-concentration isolation diffusion layer. A p-type low-concentration isolation diffusion layer for isolating the epitaxial layer into a plurality of island regions is formed in the epitaxial layer on the second high-concentration isolation diffusion layer.Type: ApplicationFiled: May 13, 2011Publication date: September 1, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Satoshi RITTAKU
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Patent number: 7960796Abstract: An n-type buried diffusion layer is formed on the surface layer of the prescribed area of a p-type silicon substrate, and a p-type first high-concentration isolation diffusion layer is formed in the silicon substrate so as to surround the buried diffusion layer. An n-type epitaxial layer is formed on the silicon substrate, the buried diffusion layer, and the first high-concentration isolation diffusion layer. A p-type second high-concentration isolation diffusion layer is formed in the epitaxial layer on the first high-concentration isolation diffusion layer. A p-type low-concentration isolation diffusion layer for isolating the epitaxial layer into a plurality of island regions is formed in the epitaxial layer on the second high-concentration isolation diffusion layer.Type: GrantFiled: November 18, 2008Date of Patent: June 14, 2011Assignee: Renesas Electronics CorporationInventor: Satoshi Rittaku
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Publication number: 20090127631Abstract: An n-type buried diffusion layer is formed on the surface layer of the prescribed area of a p-type silicon substrate, and a p-type first high-concentration isolation diffusion layer is formed in the silicon substrate so as to surround the buried diffusion layer. An n-type epitaxial layer is formed on the silicon substrate, the buried diffusion layer, and the first high-concentration isolation diffusion layer. A p-type second high-concentration isolation diffusion layer is formed in the epitaxial layer on the first high-concentration isolation diffusion layer. A p-type low-concentration isolation diffusion layer for isolating the epitaxial layer into a plurality of island regions is formed in the epitaxial layer on the second high-concentration isolation diffusion layer.Type: ApplicationFiled: November 18, 2008Publication date: May 21, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventor: Satoshi RITTAKU
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Patent number: 7462530Abstract: An n-type buried diffusion layer is formed on the surface layer of the prescribed area of a p-type silicon substrate, and a p-type first high-concentration isolation diffusion layer is formed in the silicon substrate so as to surround the buried diffusion layer. An n-type epitaxial layer is formed on the silicon substrate, the buried diffusion layer, and the first high-concentration isolation diffusion layer. A p-type second high-concentration isolation diffusion layer is formed in the epitaxial layer on the first high-concentration isolation diffusion layer. A p-type low-concentration isolation diffusion layer for isolating the epitaxial layer into a plurality of island regions is formed in the epitaxial layer on the second high-concentration isolation diffusion layer.Type: GrantFiled: December 11, 2001Date of Patent: December 9, 2008Assignee: Renesas Technology Corp.Inventor: Satoshi Rittaku
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Publication number: 20070187798Abstract: A semiconductor device including a high voltage element and a low voltage element, including: a semiconductor substrate having high voltage element region where the high voltage element is formed, and a low voltage element region where the low voltage element is formed; a first LOCOS isolation structure disposed in the high voltage element region; and a second LOCOS isolation structure disposed in the low voltage element region, wherein the first LOCOS isolation structure includes a LOCOS oxide film formed on a surface of the semiconductor substrate and a CVD oxide film formed on the LOCOS oxide film, and the second LOCOS isolation structure includes a LOCOS oxide film.Type: ApplicationFiled: December 15, 2006Publication date: August 16, 2007Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Satoshi RITTAKU, Kazuhiro Shimizu
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Publication number: 20030001210Abstract: An n-type buried diffusion layer is formed on the surface layer of the prescribed area of a p-type silicon substrate, and a p-type first high-concentration isolation diffusion layer is formed in the silicon substrate so as to surround the buried diffusion layer. An n-type epitaxial layer is formed on the silicon substrate, the buried diffusion layer, and the first high-concentration isolation diffusion layer. A p-type second high-concentration isolation diffusion layer is formed in the epitaxial layer on the first high-concentration isolation diffusion layer. A p-type low-concentration isolation diffusion layer for isolating the epitaxial layer into a plurality of island regions is formed in the epitaxial layer on the second high-concentration isolation diffusion layer.Type: ApplicationFiled: December 11, 2001Publication date: January 2, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Satoshi Rittaku