Patents by Inventor Satoshi Seto
Satoshi Seto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10784280Abstract: According to one embodiment, a semiconductor memory device includes the following structure. First conductive layers are stacked in first direction and extends in second and third directions. The first conductive layers each includes a pair of first portions, and second and third portions. The first portions extend in second direction, is provided separately from each other in third direction and includes a metal. The second portion is provided between the first portions and includes silicon. The third portion is provided on at least one side of the second portion in second direction, extends in third direction, electrically connects the first portions and includes a metal. Memory pillars extend through the second portions in first direction. Contact plugs are respectively provided on the third portion of one of the first conductive layers.Type: GrantFiled: March 6, 2019Date of Patent: September 22, 2020Assignee: Toshiba Memory CorporationInventors: Hiroyuki Ohtori, Satoshi Seto, Takashi Fukushima
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Publication number: 20200098783Abstract: According to one embodiment, a semiconductor memory device includes the following structure. First conductive layers are stacked in first direction and extends in second and third directions. The first conductive layers each includes a pair of first portions, and second and third portions. The first portions extend in second direction, is provided separately from each other in third direction and includes a metal. The second portion is provided between the first portions and includes silicon. The third portion is provided on at least one side of the second portion in second direction, extends in third direction, electrically connects the first portions and includes a metal. Memory pillars extend through the second portions in first direction. Contact plugs are respectively provided on the third portion of one of the first conductive layers.Type: ApplicationFiled: March 6, 2019Publication date: March 26, 2020Applicant: Toshiba Memory CorporationInventors: Hiroyuki Ohtori, Satoshi Seto, Takashi Fukushima
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Patent number: 10461245Abstract: According to one embodiment, a method of manufacturing a magnetic memory device, includes forming a stack film including a magnetic layer on an underlying area, forming a hard mask on the stack film, forming a stack structure by etching the stack film using the hard mask as a mask, forming a first protective insulating film on a side surface of the stack structure, and performing an oxidation treatment.Type: GrantFiled: March 3, 2015Date of Patent: October 29, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shuichi Tsubata, Masatoshi Yoshikawa, Satoshi Seto, Kazuhiro Tomioka
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Patent number: 10340311Abstract: According to one embodiment, a magnetoresistive effect element includes: a first magnetic layer; a nonmagnetic layer provided on the first magnetic layer; a second magnetic layer provided on the nonmagnetic layer; a first insulating layer provided at least on a side surface of the second magnetic layer; a second insulating layer covering at least a part of the first insulating layer; a conductive layer provided between the first insulating layer and the second insulating layer; and a first electrode including a first portion on the second magnetic layer and a second portion on a side surface of the second insulating layer. A height of a lower surface of the second portion is equal to or less than a height of an upper surface of the conductive layer.Type: GrantFiled: September 6, 2017Date of Patent: July 2, 2019Assignee: Toshiba Memory CorporationInventors: Megumi Yakabe, Satoshi Seto, Chikayoshi Kamata, Saori Kashiwada, Junichi Ito
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Patent number: 10193057Abstract: A magnetic memory device includes a stacked structure including a magnetic element, a protective insulating film covering the stacked structure, and an interface layer provided at an interface between the stacked structure and the protective insulating film. The interface layer contains a predetermined element which is not contained in the magnetic element or the protective insulating film.Type: GrantFiled: January 6, 2017Date of Patent: January 29, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masatoshi Yoshikawa, Hiroaki Yoda, Shuichi Tsubata, Kenji Noma, Tatsuya Kishi, Satoshi Seto, Kazuhiro Tomioka
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Publication number: 20190006580Abstract: A method of manufacturing a magnetic memory device includes forming a stacked structure including a magnetic element, forming a metal film which covers the stacked structure, and forming a protective insulating film formed of a metallic oxide by oxidizing the metal film. A metal element contained in the metallic oxide is selected from yttrium (Y), aluminum (Al), magnesium (Mg), calcium (Ca), zirconium (Zr) and hafnium (Hf).Type: ApplicationFiled: September 9, 2018Publication date: January 3, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Masatoshi YOSHIKAWA, Hiroaki YODA, Shuichi TSUBATA, Kenji NOMA, Tatsuya KISHI, Satoshi SETO, Kazuhiro TOMIOKA
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Patent number: 10020444Abstract: According to one embodiment, a magnetic memory device includes an interlayer insulating film, a bottom electrode formed in the interlayer insulating film, a buffer layer formed on the bottom electrode, and a stacked structure formed on the buffer layer and including a first magnetic layer functioning as a magnetic storage layer, wherein a portion of the buffer layer located on a central portion of the bottom electrode is thicker than a portion of the buffer layer located on a peripheral portion of the bottom electrode.Type: GrantFiled: March 3, 2015Date of Patent: July 10, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shuichi Tsubata, Masatoshi Yoshikawa, Satoshi Seto
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Publication number: 20180138237Abstract: According to one embodiment, a magnetoresistive effect element includes: a first magnetic layer; a nonmagnetic layer provided on the first magnetic layer; a second magnetic layer provided on the nonmagnetic layer; a first insulating layer provided at least on a side surface of the second magnetic layer; a second insulating layer covering at least a part of the first insulating layer; a conductive layer provided between the first insulating layer and the second insulating layer; and a first electrode including a first portion on the second magnetic layer and a second portion on a side surface of the second insulating layer. A height of a lower surface of the second portion is equal to or less than a height of an upper surface of the conductive layer.Type: ApplicationFiled: September 6, 2017Publication date: May 17, 2018Applicant: Toshiba Memory CorporationInventors: Megumi YAKABE, Satoshi SETO, Chikayoshi KAMATA, Saori KASHIWADA, Junichi ITO
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Publication number: 20170263860Abstract: According to one embodiment, a method of manufacturing a magnetoresistive memory device includes forming a mask on a stacked layer structure disposed on a substrate and constituting a plurality of magnetoresistive elements, etching the stacked layer structure selectively into a plurality of pillars corresponding to the mask by applying an ion beam at a first angle relative to a perpendicular direction to a surface of the substrate, removing deposited films attached to sidewalls of the pillars by applying an ion beam at a second angle greater than the first angle, and etching bottom portions of the pillars by applying an ion beam at a third angle less than the second angle.Type: ApplicationFiled: August 9, 2016Publication date: September 14, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi SETO, Minoru AMANO
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Patent number: 9698338Abstract: According to one embodiment, a method of manufacturing a magnetic memory device includes a stack structure formed of a plurality of layers including a magnetic layer, the method includes forming a lower structure film including at least one layer, etching the lower structure film to form a lower structure of the stack structure, forming an upper structure film including at least one layer on a region including the lower structure, and etching the upper structure film to form an upper structure of the stack structure on the lower structure.Type: GrantFiled: March 5, 2015Date of Patent: July 4, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masatoshi Yoshikawa, Satoshi Seto, Shuichi Tsubata, Kazuhiro Tomioka
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Publication number: 20170117454Abstract: A magnetic memory device includes a stacked structure including a magnetic element, a protective insulating film covering the stacked structure, and an interface layer provided at an interface between the stacked structure and the protective insulating film. The interface layer contains a predetermined element which is not contained in the magnetic element or the protective insulating film.Type: ApplicationFiled: January 6, 2017Publication date: April 27, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masatoshi YOSHIKAWA, Hiroaki YODA, Shuichi TSUBATA, Kenji NOMA, Tatsuya KISHI, Satoshi SETO, Kazuhiro TOMIOKA
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Magnetic memory having magnetoresistive element and method of manufacturing magnetoresistive element
Patent number: 9595663Abstract: According to one embodiment, a magnetic memory includes a transistor having first and second diffusion layers in a semiconductor substrate and a gate electrode between the first and second diffusion layers, a first insulating layer on the semiconductor substrate, the first insulating layer covering the transistor, a first contact plug in the first insulating layer, the first contact plug connected to the first diffusion layer, a second contact plug in the first insulating layer, the second contact plug connected to the second diffusion layer, a magnetoresistive element on the first insulating layer, the magnetoresistive element connected to the first contact plug, an electrode on the magnetoresistive element, and an impurity region in the first insulating layer, the second contact plug, and the electrode.Type: GrantFiled: September 5, 2014Date of Patent: March 14, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masatoshi Yoshikawa, Yasuyuki Sonoda, Satoshi Seto, Shuichi Tsubata, Kazuhiro Tomioka -
Patent number: 9570671Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including a magnetic element, a protective insulating film covering the stacked structure, and an interface layer provided at an interface between the stacked structure and the protective insulating film. The interface layer contains a predetermined element which is not contained in the magnetic element or the protective insulating film.Type: GrantFiled: September 5, 2014Date of Patent: February 14, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masatoshi Yoshikawa, Hiroaki Yoda, Shuichi Tsubata, Kenji Noma, Tatsuya Kishi, Satoshi Seto, Kazuhiro Tomioka
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Patent number: 9508922Abstract: According to one embodiment, a magnetic memory device includes a first stack structure including a first magnetic layer, and a first nonmagnetic layer provided on the first magnetic layer, a second stack structure including a second magnetic layer provided on the first nonmagnetic layer, a second nonmagnetic layer provided on the second magnetic layer, and a top conductive layer provided on the second nonmagnetic layer, and a sidewall conductive layer provided on a sidewall of the second stack structure.Type: GrantFiled: March 9, 2015Date of Patent: November 29, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masatoshi Yoshikawa, Satoshi Seto, Shuichi Tsubata, Kazuhiro Tomioka
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Patent number: 9425388Abstract: A magnetic element includes a first magnetic layer, a first non-magnetic layer on the first magnetic layer, a second magnetic layer on the first non-magnetic layer, a second non-magnetic layer on the second magnetic layer, and a third magnetic layer on the second non-magnetic layer, the third magnetic layer having a side wall layer including a material which is included in the second non-magnetic layer; wherein the material is one of Ru and Pt as a common material to the side wall layer and the second non-magnetic layer.Type: GrantFiled: March 7, 2014Date of Patent: August 23, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhiro Tomioka, Satoshi Seto, Masatoshi Yoshikawa
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Patent number: 9390350Abstract: Provided an image editing apparatus, image editing method, and a non-transitory computer readable recording medium that can faithfully visualize a degree of a position deviation amount of each page area generated at the time of a post-processing. An image editing apparatus, image editing method, and a non-transitory computer readable recording medium estimates a two-dimensional position deviation amount for each page area which is generated at the time of post-processing with respect to the printed matter based on the post-processing information relating to post-processing included in imposition data. Then, a preview image data indicating the virtual product is created by mapping a page image indicating the page area on the printed matter shifted as much as the deviation amount onto the page area on the virtual product.Type: GrantFiled: March 26, 2014Date of Patent: July 12, 2016Assignee: FUJIFILM CorporationInventor: Satoshi Seto
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Publication number: 20160079519Abstract: According to one embodiment, a method of manufacturing a magnetic memory device includes a stack structure formed of a plurality of layers including a magnetic layer, the method includes forming a lower structure film including at least one layer, etching the lower structure film to form a lower structure of the stack structure, forming an upper structure film including at least one layer on a region including the lower structure, and etching the upper structure film to form an upper structure of the stack structure on the lower structure.Type: ApplicationFiled: March 5, 2015Publication date: March 17, 2016Inventors: Masatoshi YOSHIKAWA, Satoshi SETO, Shuichi TSUBATA, Kazuhiro TOMIOKA
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Publication number: 20160072047Abstract: According to one embodiment, a semiconductor memory device includes a lower electrode, an MTJ element, a cap layer and an upper electrode. The lower electrode is provided above a semiconductor substrate. The MTJ element is provided above the lower electrode. The cap layer is provided above the MTJ element and is oxygen-free. The upper electrode is connected to the cap layer.Type: ApplicationFiled: February 23, 2015Publication date: March 10, 2016Inventors: Satoshi SETO, Masatoshi YOSHIKAWA, Shuichi TSUBATA, Kazuhiro TOMIOKA
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Publication number: 20160072050Abstract: According to one embodiment, a magnetic memory device includes a first stack structure including a first magnetic layer, and a first nonmagnetic layer provided on the first magnetic layer, a second stack structure including a second magnetic layer provided on the first nonmagnetic layer, a second nonmagnetic layer provided on the second magnetic layer, and a top conductive layer provided on the second nonmagnetic layer, and a sidewall conductive layer provided on a sidewall of the second stack structure.Type: ApplicationFiled: March 9, 2015Publication date: March 10, 2016Inventors: Masatoshi YOSHIKAWA, Satoshi SETO, Shuichi TSUBATA, Kazuhiro TOMIOKA
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Publication number: 20160072055Abstract: According to one embodiment, a manufacturing method of a semiconductor memory device includes the following steps. The method includes forming a first magnetic layer, a second magnetic layer, and an insulating layer therebetween, forming a mask layer on the second magnetic layer, etching the second magnetic layer, the insulating layer, and the first magnetic layer using the mask layer as a mask and forming a magnetic tunnel junction (MTJ) element, and performing oxidation a sidewall of the MTJ element with H2O.Type: ApplicationFiled: February 24, 2015Publication date: March 10, 2016Inventors: Satoshi SETO, Shuichi TSUBATA, Masatoshi YOSHIKAWA, Kazuhiro TOMIOKA