Patents by Inventor Satoshi Shigenaga
Satoshi Shigenaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8902240Abstract: An image processing device improves processing performance at low cost. The image processing device is provided with a memory controller that divides up and assigns banks accessed by a video inputter, a drawer, and a video outputter to multiple frame memories. The image processing device arbitrates access requests from master units, such as the video inputter, the drawer, and the video outputter, and controls data transmission so that the multiple master units can access both the frame memories in parallel.Type: GrantFiled: August 11, 2009Date of Patent: December 2, 2014Assignee: Panasonic CorporationInventor: Satoshi Shigenaga
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Publication number: 20110134133Abstract: Provided is an image processing device with which processing performance can be improved at low cost. The image processing device (100) is provided with a memory controller (190) that divides up and assigns banks accessed by a video input unit (140), a drawing unit (150), and a video output unit (160) to multiple frame memories (120, 130), arbitrates access requests from the master units, i.e., the video input unit (140), the drawing unit (150), and the video output unit (160), and controls data transmission so that the multiple master units can access both the frame memories (120, 130) in parallel.Type: ApplicationFiled: August 11, 2009Publication date: June 9, 2011Applicant: PANASONIC CORPORATIONInventor: Satoshi Shigenaga
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Patent number: 7667714Abstract: A patterned polygon rendering apparatus has an edge dot attribute setting section 1 that assigns an attribute dot, which indicates an edge of a polygon, to respective dots located in an edge line of the polygon and stores the assigned attribute dots in work memory 2 on a per-dot basis, to thus perform edge processing; an internal attribute dot setting section 3 that assigns an attribute dot, which indicates the inside of the polygon, to respective dots located in an internal region of the polygon by reference to the work memory 2 and stores the assigned attribute dots into the work memory 2, to thus perform painting processing; and a pattern setting section 4 that sets edge color data to the dots assigned the attribute dots, which indicate the edges of the polygon, by reference to the work memory 2, sets pattern data to the dots assigned the attribute dots indicating the inside of the polygon, and renders the data stored in the work memory 2 to the frame memory 6, to thus perform pattern setting processing.Type: GrantFiled: January 31, 2006Date of Patent: February 23, 2010Assignee: Panasonic CorporationInventor: Satoshi Shigenaga
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Patent number: 7646385Abstract: When a plurality of coplanar shapes are rendered over one another by performing a hidden surface removal operation using the Z value, a reference plane is specified, and the Z value of each point of a shape to be rendered on the reference plane is uniquely calculated based on the Z value of the rendering start point, the Z value gradient dZdx for the X direction, and the Z value gradient dZdy for the Y direction. Thus, any coplanar shapes will have the same Z value for each point shared therebetween. Therefore, if the rendering process is performed under such a rule that a shape is overwritten when the Z value of the new shape is less than or equal to the current Z value, it is ensured that the previously-rendered shape is always overwritten with a later-rendered, coplanar shape. Thus, it is possible to prevent a phenomenon that some pixels of a later-rendered shape that are supposed to be displayed are not displayed.Type: GrantFiled: July 5, 2006Date of Patent: January 12, 2010Assignee: Panasonic CorporationInventors: Shigeaki Mido, Satoshi Shigenaga
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Publication number: 20090281727Abstract: A car navigation system capable of performing both real-time route guidance for a driver, and non-route-guidance display and operation of car navigation functions such as destination setting and vicinity searching for a non-driver, without necessitating a high-speed CPU or a high-performance drawing processing section. A display apparatus 200 is equipped with a CPU 210, an operating section 220, and drawing processing sections 230 and 240 corresponding to two display screens 250A and 250B, navigation-related processing is performed in a navigation apparatus 100, and drawing processing for the driver and drawing processing for a non-driver are executed independently by drawing processing sections 230 and 240 respectively of display apparatus 200. Functions are shared between navigation apparatus 100 and display apparatus 200.Type: ApplicationFiled: May 6, 2008Publication date: November 12, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Yoshinori NAGATANI, Satoshi SHIGENAGA, Shigeaki MIDO
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Patent number: 7391480Abstract: An image processing apparatus carrying out a gamma correction for input data includes polygonal line approximating apparatus for carrying out the gamma correction by a polygonal line approximation, a look-up table partially storing gamma correction data corresponding to the input data, and a correction deciding portion and a selector which select the output of one of the polygonal line approximating apparatus and the look-up table corresponding to the input data.Type: GrantFiled: March 10, 2005Date of Patent: June 24, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tetsu Fukue, Satoshi Shigenaga
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Patent number: 7365751Abstract: A memory write section 2 writes texture data in a number capable of being transferred at a time and written in one address, in one of first through fourth texture memories 1a through 1d in common by single write operation. If the V coordinate of texture data to be written is an even number, the texture data is written in the first, second, third and fourth texture memories 1a, 1b, 1c and 1d in this order. If the V coordinate is an odd number, the data is written in the third, fourth, first and second texture memories 1c, 1d, 1a and 1b in this order.Type: GrantFiled: November 9, 2004Date of Patent: April 29, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Satoshi Shigenaga
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Publication number: 20070008316Abstract: When a plurality of coplanar shapes are rendered over one another by performing a hidden surface removal operation using the Z value, a reference plane is specified, and the Z value of each point of a shape to be rendered on the reference plane is uniquely calculated based on the Z value of the rendering start point, the Z value gradient dZdx for the X direction, and the Z value gradient dZdy for the Y direction. Thus, any coplanar shapes will have the same Z value for each point shared therebetween. Therefore, if the rendering process is performed under such a rule that a shape is overwritten when the Z value of the new shape is less than or equal to the current Z value, it is ensured that the previously-rendered shape is always overwritten with a later-rendered, coplanar shape. Thus, it is possible to prevent a phenomenon that some pixels of a later-rendered shape that are supposed to be displayed are not displayed.Type: ApplicationFiled: July 5, 2006Publication date: January 11, 2007Inventors: Shigeaki Mido, Satoshi Shigenaga
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Publication number: 20060170694Abstract: A patterned polygon rendering apparatus has an edge dot attribute setting section 1 that assigns an attribute dot, which indicates an edge of a polygon, to respective dots located in an edge line of the polygon and stores the assigned attribute dots in work memory 2 on a per-dot basis, to thus perform edge processing; an internal attribute dot setting section 3 that assigns an attribute dot, which indicates the inside of the polygon, to respective dots located in an internal region of the polygon by reference to the work memory 2 and stores the assigned attribute dots into the work memory 2, to thus perform painting processing; and a pattern setting section 4 that sets edge color data to the dots assigned the attribute dots, which indicate the edges of the polygon, by reference to the work memory 2, sets pattern data to the dots assigned the attribute dots indicating the inside of the polygon, and renders the data stored in the work memory 2 to the frame memory 6, to thus perform pattern setting processing.Type: ApplicationFiled: January 31, 2006Publication date: August 3, 2006Inventor: Satoshi Shigenaga
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Patent number: 7075549Abstract: By making it possible to freely change calculations of as well as variables that are input into the same calculation circuits, dedicated circuits corresponding to rendering functions become unnecessary, and in order to realize multi-functional rendering with circuitry of a small scale, a graphic image rendering apparatus includes a rendering information generation portion that generates rendering parameters corresponding to X and Y coordinates of pixels constituting a graphic image, a pixel calculation portion that, for each pixel, makes a selection as appropriate from the rendering parameters and a constant and performs a calculation, and a memory interface portion that writes a calculation result of the pixel calculation portion into a frame memory.Type: GrantFiled: June 9, 2005Date of Patent: July 11, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Satoshi Shigenaga
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Patent number: 7015923Abstract: To provide an apparatus for painting figures which is improved in painting capability better than the conventional art even when a path to an external memory section is narrow. In order to simultaneously write previously generated painting information and read data required for generating painting information later in the painting coordinate generating section and the painting information generating section on the painting apparatus, while painting information is generated, first and second buffers are provided as a buffer section for storing painting information generated in the painting information generating section, and address information storing sections corresponding to the first and second buffers are provided as an address generating section for generating an address for storing painting information, which is accumulated in the buffer section, in an external memory section.Type: GrantFiled: September 14, 2001Date of Patent: March 21, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Satoshi Shigenaga, Tomohiro Okada, Tadashi Okamoto
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Patent number: 6965382Abstract: By making it possible to freely change calculations of as well as variables that are input into the same calculation circuits, dedicated circuits corresponding to rendering functions become unnecessary, and in order to realize multi-functional rendering with circuitry of a small scale, a graphic image rendering apparatus includes a rendering information generation portion that generates rendering parameters corresponding to X and Y coordinates of pixels constituting a graphic image, a pixel calculation portion that, for each pixel, makes a selection as appropriate from the rendering parameters and a constant and performs a calculation, and a memory interface portion that writes a calculation result of the pixel calculation portion into a frame memory.Type: GrantFiled: March 3, 2003Date of Patent: November 15, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Satoshi Shigenaga
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Publication number: 20050237332Abstract: To increase the responsibility of the system by reducing the time occupied by memory means. An information processor includes an instruction parallel processor that executes the process by accessing a local memory, at least one function block that accesses the local memory, and a local memory interface that transfers data in split form from the local memory to the instruction parallel processor.Type: ApplicationFiled: April 22, 2005Publication date: October 27, 2005Inventors: Toru Matsui, Satoshi Shigenaga
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Publication number: 20050225555Abstract: By making it possible to freely change calculations of as well as variables that are input into the same calculation circuits, dedicated circuits corresponding to rendering functions become unnecessary, and in order to realize multi-functional rendering with circuitry of a small scale, a graphic image rendering apparatus includes a rendering information generation portion that generates rendering parameters corresponding to X and Y coordinates of pixels constituting a graphic image, a pixel calculation portion that, for each pixel, makes a selection as appropriate from the rendering parameters and a constant and performs a calculation, and a memory interface portion that writes a calculation result of the pixel calculation portion into a frame memory.Type: ApplicationFiled: June 9, 2005Publication date: October 13, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Satoshi Shigenaga
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Publication number: 20050200761Abstract: An image processing apparatus carrying out a gamma correction for input data includes polygonal line approximating means for carrying out the gamma correction by a polygonal line approximation, a look-up table partially storing gamma correction data corresponding to the input data, and a correction deciding portion and a selector which select the output of one of the polygonal line approximating means and the look-up table corresponding to the input data.Type: ApplicationFiled: March 10, 2005Publication date: September 15, 2005Inventors: Tetsu Fukue, Satoshi Shigenaga
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Publication number: 20050104891Abstract: A memory write section 2 writes texture data in a number capable of being transferred at a time and written in one address, in one of first through fourth texture memories 1a through 1d in common by single write operation. If the V coordinate of texture data to be written is an even number, the texture data is written in the first, second, third and fourth texture memories 1a, 1b, 1c and 1d in this order. If the V coordinate is an odd number, the data is written in the third, fourth, first and second texture memories 1c, 1d, 1a and 1b in this order.Type: ApplicationFiled: November 9, 2004Publication date: May 19, 2005Inventor: Satoshi Shigenaga
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Publication number: 20030193507Abstract: By making it possible to freely change calculations of as well as variables that are input into the same calculation circuits, dedicated circuits corresponding to rendering functions become unnecessary, and in order to realize multi-functional rendering with circuitry of a small scale, a graphic image rendering apparatus includes a rendering information generation portion that generates rendering parameters corresponding to X and Y coordinates of pixels constituting a graphic image, a pixel calculation portion that, for each pixel, makes a selection as appropriate from the rendering parameters and a constant and performs a calculation, and a memory interface portion that writes a calculation result of the pixel calculation portion into a frame memory.Type: ApplicationFiled: March 3, 2003Publication date: October 16, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Satoshi Shigenaga
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Patent number: 6504543Abstract: A polygon drawing apparatus for drawing a polygon which is colored inside its outline by using outline data indicating the outline of the polygon, the apparatus comprising: an outline data generation unit for generating outline data indicating the outline of the polygon on the basis of coordinate data indicating the coordinates of points constituting the polygon; a mask data generation unit for performing, for a predetermined amount of the outline data, parallel exclusive-OR processes in units of amounts constituting the predetermined amount, thereby generating mask data which specifies “coloring” for the inside of the outline; and a segment generation unit for drawing the polygon by using the mask data generated by the mask data generation means. Therefore, this polygon drawing apparatus can provide a satisfactory result of display without using a bulk memory, and without increasing the processing load.Type: GrantFiled: January 5, 2000Date of Patent: January 7, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tadashi Okamoto, Satoshi Shigenaga
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Publication number: 20020039102Abstract: To provide an apparatus for painting figures which is improved in painting capability better than the conventional art even when a path to an external memory section is narrow. In order to simultaneously write previously generated painting information and read data required for generating painting information later in the painting coordinate generating section and the painting information generating section on the painting apparatus, while painting information is generated, first and second buffers are provided as a buffer section for storing painting information generated in the painting information generating section, and address information storing sections corresponding to the first and second buffers are provided as an address generating section for generating an address for storing painting information, which is accumulated in the buffer section, in an external memory section.Type: ApplicationFiled: September 14, 2001Publication date: April 4, 2002Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Satoshi Shigenaga, Tomohiro Okada, Tadashi Okamoto
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Patent number: 6295073Abstract: A vertex processing unit is provided for labeling each selected vertex dot as a vertical or horizontal attribute dot based on the direction of a side vector terminating at the vertex dot selected and that of a side vector originating from the vertex dot selected. A contour line segment processing unit is also provided for labeling each edge dot selected from a side as a vertical attribute dot if the y coordinate of the edge dot selected is different from that of a previous edge dot and that of a vertex dot located at the terminal point of the side, or otherwise, as a horizontal attribute dot. Contour color data are defined for the dots labeled as vertical or horizontal attribute dots. And inner color data are defined for the dots existing between an odd-numbered vertical attribute dot and an even-numbered vertical attribute dot, which is next to the former dot, on a selected scan line parallel to the axis of x coordinates, except for horizontal attribute dots.Type: GrantFiled: June 4, 1999Date of Patent: September 25, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Satoshi Shigenaga