Patents by Inventor Satoshi Takashima
Satoshi Takashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11785340Abstract: A signal processing device according to the present technology includes a stacked auto encoder that processes an input signal from a sensor, a control line associated learner including a neural network and subjected to control line associated learning for performing learning by associating different event aspects related to a specific event with values of different control lines with a feature quantity obtained in an intermediate layer of the stacked auto encoder after pretraining as an input, and a refactorer that obtains a difference between a first output that is an output of the control line associated learner when a first value is given to the control line, and a second output that is an output of the control line associated learner when a second value different from the first value is given to the control line.Type: GrantFiled: February 10, 2021Date of Patent: October 10, 2023Assignees: SONY SEMICONDUCTOR SOLUTIONS CORPORATION, SONY GROUP CORPORATIONInventors: Hiroshi Arai, Yuriko Ohtsuka, Kenichiro Nishi, Takeshi Masuura, Norimitsu Okiyama, Yuji Matsui, Satoshi Takashima
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Publication number: 20230308759Abstract: A signal processing device includes an approximate curved surface conversion unit that includes a first stacked autoencoder pretrained on the basis of learning input data constituted by coordinate data acquired for each of multiple elements of an object, and that obtains approximate curved surface data indicating an approximate curved surface of the object in an intermediate layer of the first stacked autoencoder, on the basis of input data constituted by the coordinate data acquired for each of the elements, and a geometric modulation processing unit that includes a second stacked autoencoder having learned by machine learning on the basis of learning input data constituted by the approximate curved surface data and on the basis of training data constituted by a result obtained by coordinate conversion for each of the elements in a geometric modulation process performed for the object, and performs the geometric modulation process.Type: ApplicationFiled: April 20, 2021Publication date: September 28, 2023Applicant: Sony Semiconductor Solutions CorporationInventors: Hiroshi ARAI, Yuriko OHTSUKA, Kenichiro NISHI, Takeshi MASUURA, Norimitsu OKIYAMA, Yuji MATSUI, Satoshi TAKASHIMA
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Publication number: 20230156331Abstract: A signal processing device according to the present technology includes a feature quantity extraction unit including a neural network and trained to extract a feature quantity for a specific event with respect to an input signal from a sensor. and a correction unit that performs correction of the input signal on the basis of the feature quantity extracted by the feature quantity extraction unit.Type: ApplicationFiled: February 10, 2021Publication date: May 18, 2023Applicants: Sony Semiconductor Solutions Corporation, Sony Group CorporationInventors: Hiroshi ARAI, Yuriko OHTSUKA, Kenichiro NISHI, Takeshi MASUURA, Norimitsu OKIYAMA, Yuji MATSUI, Satoshi TAKASHIMA
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Publication number: 20230135628Abstract: A signal processing device according to the present technology includes a stacked auto encoder that processes an input signal from a sensor, a control line associated learner including a neural network and subjected to control line associated learning for performing learning by associating different event aspects related to a specific event with values of different control lines with a feature quantity obtained in an intermediate layer of the stacked auto encoder after pretraining as an input, and a refactorer that obtains a difference between a first output that is an output of the control line associated learner when a first value is given to the control line, and a second output that is an output of the control line associated learner when a second value different from the first value is given to the control line.Type: ApplicationFiled: February 10, 2021Publication date: May 4, 2023Applicants: Sony Semiconductor Solutions Corporation, Sony Group CorporationInventors: Hiroshi ARAI, Yuriko OHTSUKA, Kenichiro NISHI, Takeshi MASUURA, Norimitsu OKIYAMA, Yuji MATSUI, Satoshi TAKASHIMA
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Publication number: 20230108850Abstract: A signal processing apparatus includes: a data input unit to which image data is input; an output unit configured to output an output value based on the data input to the data input unit; an expectation feedback calculator configured to calculate a difference between an expectation based on the input data and the output value; and a Bayesian estimator to which information on the difference and information based on the image data are input and which is configured to perform machine learning in order to approximate the output value to the expectation based on the input information and to search for an optimum configuration.Type: ApplicationFiled: February 10, 2021Publication date: April 6, 2023Applicants: Sony Semiconductor Solutions Corporation, Sony Group CorporationInventors: Hiroshi ARAI, Yuriko OHTSUKA, Kenichiro NISHI, Takeshi MASUURA, Norimitsu OKIYAMA, Yuji MATSUI, Satoshi TAKASHIMA
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Patent number: 11200059Abstract: A processor includes: an instruction fetch portion configured to fetch simultaneously a plurality of fixed-length instructions in accordance with a program counter; an instruction predecoder configured to predecode specific fields in a part of the plurality of fixed-length instructions; and a program counter management portion configured to control an increment of the program counter in accordance with a result of the predecoding.Type: GrantFiled: June 2, 2017Date of Patent: December 14, 2021Assignee: SONY CORPORATIONInventors: Hirokazu Hanaki, Satoshi Takashima
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Patent number: 9841978Abstract: A processor includes: an instruction fetch portion configured to fetch simultaneously a plurality of fixed-length instructions in accordance with a program counter; an instruction predecoder configured to predecode specific fields in a part of the plurality of fixed-length instructions; and a program counter management portion configured to control an increment of the program counter in accordance with a result of the predecoding.Type: GrantFiled: July 22, 2011Date of Patent: December 12, 2017Assignee: Sony CorporationInventors: Hirokazu Hanaki, Satoshi Takashima
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Publication number: 20170277540Abstract: A processor includes: an instruction fetch portion configured to fetch simultaneously a plurality of fixed-length instructions in accordance with a program counter; an instruction predecoder configured to predecode specific fields in a part of the plurality of fixed-length instructions; and a program counter management portion configured to control an increment of the program counter in accordance with a result of the predecoding.Type: ApplicationFiled: June 2, 2017Publication date: September 28, 2017Inventors: Hirokazu Hanaki, Satoshi Takashima
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Patent number: 9164763Abstract: An information processing apparatus includes an instruction supplying section that supplies a plurality of instructions as a single instruction group, an executing section that repetitively executes a plurality of execution processes corresponding to the plurality of instructions in parallel, an issue timing control section that controls an issue timing of each of the instructions to the executing section so that the plurality of execution processes are executed with a timing delayed in accordance with a predetermined latency, and an operand transforming section that transforms an operand register address of each of the instructions in accordance with a predetermined increment value upon every repetition of execution in the executing section.Type: GrantFiled: August 24, 2010Date of Patent: October 20, 2015Assignee: SONY CORPORATIONInventors: Satoshi Takashima, Hirokazu Hanaki
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Patent number: 8774292Abstract: A data transfer system includes a transmission circuit, which operates by a first clock signal, and a receiving circuit, which operates by a second clock signal different from the first clock signal. The transmission circuit includes an output circuit that outputs a poll signal, of which a level is logically inverted in accordance with a transmission timing of transmission data from the transmission circuit to the receiving circuit. A first signal generating circuit receives the transmission data at a plurality of timings and generates plural sets of reception data corresponding to the plurality of timings. A second signal generating circuit receives the poll signal at the plurality of timings and generates synchronous poll signals corresponding to the plurality of timings. A data selecting circuit compares levels of the synchronous poll signals with each other and selects one of the sets of reception data based on the comparison result.Type: GrantFiled: November 7, 2012Date of Patent: July 8, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Satoshi Takashima
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Patent number: 8349145Abstract: The present invention provides the technology for burying metal even in a fine concave portion such as trench and via. According to an embodiment of the present invention, a vapor of the metal as the objective material, a gas containing halogen for etching the metal, and a metal halide vapor made up of the metal element and the halogen element are supplied to the substrate, which thus forms a metal halide layer in the concave portion, and thereby deposits the metal under the metal halide layer. The procedure can achieve the above object.Type: GrantFiled: August 13, 2010Date of Patent: January 8, 2013Assignee: Canon Anelva CorporationInventors: Suguru Noda, Satoshi Takashima
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Patent number: 8255668Abstract: An interface includes a controller that divides a burst access command into a plurality of command cycles and supplies the plurality of command cycles to a storage device including a plurality of blocks, and a block address converter that outputs an address at a first command cycle of the plurality of command cycles. The address is obtained by shifting at least one bit of an external block address input in response to the burst access command. The address is supplied to the storage device at the first command cycle, and the external block address is supplied to the storage device at a command cycle other than the first command cycle.Type: GrantFiled: January 22, 2010Date of Patent: August 28, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Shinya Ohhashi, Satoshi Takashima, Akihiro Miki
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Publication number: 20120066480Abstract: A processor includes: an instruction fetch portion configured to fetch simultaneously a plurality of fixed-length instructions in accordance with a program counter; an instruction predecoder configured to predecode specific fields in a part of the plurality of fixed-length instructions; and a program counter management portion configured to control an increment of the program counter in accordance with a result of the predecoding.Type: ApplicationFiled: July 22, 2011Publication date: March 15, 2012Applicant: Sony CorporationInventors: Hirokazu Hanaki, Satoshi Takashima
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Publication number: 20110099354Abstract: An information processing apparatus includes an instruction supplying section that supplies a plurality of instructions as a single instruction group, an executing section that repetitively executes a plurality of execution processes corresponding to the plurality of instructions in parallel, an issue timing control section that controls an issue timing of each of the instructions to the executing section so that the plurality of execution processes are executed with a timing delayed in accordance with a predetermined latency, and an operand transforming section that transforms an operand register address of each of the instructions in accordance with a predetermined increment value upon every repetition of execution in the executing section.Type: ApplicationFiled: August 24, 2010Publication date: April 28, 2011Applicant: Sony CorporationInventors: Satoshi Takashima, Hirokazu Hanaki
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Publication number: 20110031107Abstract: The present invention provides the technology for burying metal even in a fine concave portion such as trench and via. According to an embodiment of the present invention, a vapor of the metal as the objective material, a gas containing halogen for etching the metal, and a metal halide vapor made up of the metal element and the halogen element are supplied to the substrate, which thus forms a metal halide layer in the concave portion, and thereby deposits the metal under the metal halide layer. The procedure can achieve the above object.Type: ApplicationFiled: August 13, 2010Publication date: February 10, 2011Applicants: CANON ANELVA CORPORATIONInventors: Suguru NODA, Satoshi Takashima
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Publication number: 20100250872Abstract: An interface includes a controller that divides a burst access command into a plurality of command cycles and supplies the plurality of command cycles to a storage device including a plurality of blocks, and a block address converter that outputs an address at a first command cycle of the plurality of command cycles. The address is obtained by shifting at least one bit of an external block address input in response to the burst access command. The address is supplied to the storage device at the first command cycle, and the external block address is supplied to the storage device at a command cycle other than the first command cycle.Type: ApplicationFiled: January 22, 2010Publication date: September 30, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Shinya OHHASHI, Satoshi Takashima, Akihiro Miki
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Patent number: 7395408Abstract: The parallel execution processor 100 fetches a piece of instruction data. When the piece of instruction data includes only one instruction, the instruction decoding unit 120 assigns the one instruction to all the PEs. When the piece of instruction data includes two instructions, the instruction decoding unit 120 forms all the PEs into two groups, so as to assign one instruction to each group. By making it possible to execute, in parallel, not only one type of instruction but also instructions that are different from each other, it is possible to improve the utilization efficiency of the parallel execution processor 100.Type: GrantFiled: October 16, 2003Date of Patent: July 1, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takeshi Tanaka, Satoshi Takashima, Hideshi Nishida, Kozo Kimura, Tokuzo Kiyohara
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Patent number: 7315934Abstract: A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and the arithmetic logic units of the processing elements. The network unit has a selector for simultaneously performing a plurality of data transfers which are each made from a register file of one processing element to an operation unit of another processing element. With the provision of this selector that can perform such simultaneous data transfers, the processing efficiency of the processing elements can be maintained even if a change occurs in operand assignments and the like.Type: GrantFiled: February 28, 2003Date of Patent: January 1, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroyuki Morishita, Atsushi Ito, Satoshi Takashima, Hideshi Nishida, Kozo Kimura, Tokuzo Kiyohara, Akira Miyoshi, Hiroshi Kadota
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Patent number: 7020787Abstract: A microprocessor comprises a calculation unit that (i) includes partial calculation units each operable to perform partial data calculation, and (ii) is operable to perform data calculation on N or less bits, where N is a total number of bits on which the partial calculation units are to perform data calculation. The microprocessor, when having the calculation unit perform data calculation according to an instruction fetched from a memory, controls the partial calculation units depending on a bit width mode selected in terms of a number of bits on which data calculation is to be performed, so as to either (i) have all the partial calculation units operate, or (ii) suspend operation of a predetermined number of the partial calculation units, and have the rest of the partial calculation units operate.Type: GrantFiled: December 18, 2002Date of Patent: March 28, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Satoshi Takashima, Hideshi Nishida, Kozo Kimura, Tokuzo Kiyohara
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Publication number: 20040133765Abstract: The parallel execution processor 100 fetches a piece of instruction data. When the piece of instruction data includes only one instruction, the instruction decoding unit 120 assigns the one instruction to all the PEs. When the piece of instruction data includes two instructions, the instruction decoding unit 120 forms all the PEs into two groups, so as to assign one instruction to each group. By making it possible to execute, in parallel, not only one type of instruction but also instructions that are different from each other, it is possible to improve the utilization efficiency of the parallel execution processor 100.Type: ApplicationFiled: October 16, 2003Publication date: July 8, 2004Inventors: Takeshi Tanaka, Satoshi Takashima, Hideshi Nishida, Kozo Kimura, Tokuzo Kiyohara