Abstract: A semiconductor device includes: an insulating substrate; a first electrode pattern and a second electrode pattern provided apart from each other on a major surface of the insulating substrate; a semiconductor element connected to the first electrode pattern; an electrode terminal connected to the second electrode pattern; and a connection wiring. The connection wiring electrically connects the first electrode pattern and the second electrode pattern with each other and has a thermal resistance larger than that of the first electrode pattern.

Abstract: A semiconductor device includes: an insulating substrate; a first electrode pattern and a second electrode pattern provided apart from each other on a major surface of the insulating substrate; a semiconductor element connected to the first electrode pattern; an electrode terminal connected to the second electrode pattern; and a connection wiring. The connection wiring electrically connects the first electrode pattern and the second electrode pattern with each other and has a thermal resistance larger than that of the first electrode pattern.

Abstract: According to one embodiment, a semiconductor device includes a base substrate, at least one semiconductor chip provided above the base substrate, and a resin case covering the semiconductor chip and supported by the base substrate. A partition plate holds back extension of a crack occurring in the resin case being provided in the resin case.

Abstract: An insulated gate semiconductor device, includes an isolating structure shaped in a circulating section along the periphery of a semiconductor substrate to isolate that part from an inside device region, a peripheral diffusion region of the semiconductor substrate located outside the isolating structure, a plurality of cell structures defined in the inside device region and divided in segments by insulated trench-shaped gates to have a base region covered with an emitter region in its upper surface, a collector region, and an emitter electrode electrically connected to the emitter region and the base region, a dummy base region contiguous to the cell structures and configured as a base region that has its upper surface left without the emitter region connected to the emitter electrode, an inner region defined in and insulated from the dummy base region, and a connection part to electrically connect the inner region to the emitter electrode.

Abstract: A power semiconductor device according to the present invention comprises: a first conductive type base layer; a second conductive type base layer selectively formed on the first conductive type base layer; an insulation layer formed in the region on the first conductive type base layer on which the second conductive type base layer is not formed; a gate insulation film formed on the inner surface of a trench formed between the second conductive type base layer and the insulation layer so as to separate them from each other and to reach the first conductive type base layer from the surface of the second conductive type base layer; a first conductive type source layer selectively formed on the surface of the second conductive type base layer in contact with the gate insulation film; a gate electrode formed in the trench and insulated from the first conductive type base layer, the second conductive type base layer, and the first conductive type source layer by the gate insulation film; a main electrode electric

Abstract: An insulated gate semiconductor device, includes an isolating structure shaped in a circulating section along the periphery of a semiconductor substrate so as to isolate that part from an inside device region, a peripheral diffusion region of the semiconductor substrate located outside the isolating structure, a plurality of cell structures defined in the device region and divided in segments by insulated trench-shaped gates so as to have a base region covered with an emitter region in its upper surface, a collector region, and an emitter electrode electrically connected to the emitter region and the base region, a dummy base region contiguous to the cell structures and configured as a base region that has its upper surface left without the emitter region connected to the emitter electrode, and a connection part to electrically connect the peripheral diffusion region to the emitter electrode.

Abstract: IGBT chips and FRD chips are arranged on the same plane so as to be press-contacted by an emitter press-contact electrode plate and a collector press-contact electrode plate at the same time. The FRD chips are arranged at a central portion, and the IGBT chips are arranged at the peripheral portion of the FRD chips. A resin substrate having an opening in its contact portion between a main surface of each of said chip and the emitter press-contact electrode plate is provided between both press-contact electrode plates. Gate press-contact electrodes are formed on the resin substrate to be electrically connected to a gate electrode of each of the IGBT chips. Also, gate wires are fixed to the resin substrate to supply a control signal for controlling the IGBT chips to the gate electrode of the IGBT chips from the gate wires through the gate press-contact electrode.