Patents by Inventor Satoshi Tobe

Satoshi Tobe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8728870
    Abstract: Provided are a thin film silicon wafer having high gettering capability, a manufacturing method therefor, a multi-layered silicon wafer formed by laminating the thin film silicon wafers, and a manufacturing method therefor. The thin film silicon wafer is manufactured by: forming one or more gettering layers immediately below a device layer which is formed in a vicinity of a front surface of a semiconductor silicon wafer; fabricating a device in the device layer of the semiconductor silicon wafer; and after the device has been fabricated, removing part of the semiconductor silicon wafer from a rear surface thereof to immediately below the gettering layers so as to leave at least one of the gettering layers in place. As a result, the thin film silicon wafer is allowed to have gettering capability even after having been reduced in thickness to be in a thin film form.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: May 20, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Satoshi Tobe, Takao Takenaka
  • Patent number: 8043871
    Abstract: The present invention provides a method for forming an oxide film on a silicon wafer, comprising: measuring surface roughness of the silicon wafer and/or crystallinity in a surface layer portion of the silicon wafer in advance; adjusting oxidizing conditions for the silicon wafer based on the measurement value; and forming the oxide film on the silicon wafer under the adjusted oxidizing conditions. As a result, there can be provided the method for forming an oxide film by which the oxidizing conditions can be adjusted based on a state of the surface and/or the surface layer of the silicon wafer before forming the oxide film and even an ultrathin oxide film can be thereby accurately formed.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: October 25, 2011
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tsuyoshi Ohtsuki, Satoshi Tobe, Yasushi Mizusawa
  • Publication number: 20110033958
    Abstract: The present invention provides a method for forming an oxide film on a silicon wafer, comprising: measuring surface roughness of the silicon wafer and/or crystallinity in a surface layer portion of the silicon wafer in advance; adjusting oxidizing conditions for the silicon wafer based on the measurement value; and forming the oxide film on the silicon wafer under the adjusted oxidizing conditions. As a result, there can be provided the method for forming an oxide film by which the oxidizing conditions can be adjusted based on a state of the surface and/or the surface layer of the silicon wafer before forming the oxide film and even an ultrathin oxide film can be thereby accurately formed.
    Type: Application
    Filed: March 24, 2009
    Publication date: February 10, 2011
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tsuyoshi Ohtsuki, Satoshi Tobe, Yasushi Mizusawa
  • Publication number: 20100171195
    Abstract: Provided are a thin film silicon wafer having high gettering capability, a manufacturing method therefor, a multi-layered silicon wafer formed by laminating the thin film silicon wafers, and a manufacturing method therefor. The thin film silicon wafer is manufactured by: forming one or more gettering layers immediately below a device layer which is formed in a vicinity of a front surface of a semiconductor silicon wafer; fabricating a device in the device layer of the semiconductor silicon wafer; and after the device has been fabricated, removing part of the semiconductor silicon wafer from a rear surface thereof to immediately below the gettering layers so as to leave at least one of the gettering layers in place. As a result, the thin film silicon wafer is allowed to have gettering capability even after having been reduced in thickness to be in a thin film form.
    Type: Application
    Filed: June 4, 2008
    Publication date: July 8, 2010
    Applicant: SHIN-ETSU HANDOTAI CO., LTD
    Inventors: Satoshi Tobe, Takao Takenaka
  • Patent number: 7713851
    Abstract: A silicon epitaxial layer 2 is grown in vapor phase on a silicon single crystal substrate 1 manufactured by the Czochralski method, and doped with boron so as to adjust the resistivity to 0.02 ?·cm or below, oxygen precipitation nuclei 11 are formed in the silicon single crystal substrate 1, by carrying out annealing at 450° C. to 750° C., in an oxidizing atmosphere, for a duration of time allowing formation of a silicon oxide film only to as thick as 2 nm or below on the silicon epitaxial layer 2 as a result of the annealing, and thus-formed silicon oxide film 3 is etched as the first cleaning after the low-temperature annealing, using a cleaning solution. By this process, the final residual thickness of the silicon oxide film can be suppressed only to a level equivalent to native oxide film, without relying upon the hydrofluoric acid cleaning.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: May 11, 2010
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Fumitaka Kume, Tomosuke Yoshida, Ken Aihara, Ryoji Hoshi, Satoshi Tobe, Naohisa Toda, Fumio Tahara
  • Publication number: 20080038526
    Abstract: A silicon epitaxial wafer 100 formed by growing a silicon epitaxial layer 2 on a silicon single crystal substrate 1, produced by a CZ method, and doped with boron so that a resistivity thereof is in the range of 0.009 ?·cm or higher and 0.012 ?·cm or lower. The silicon single crystal substrate 1 has a density of the oxygen precipitation nuclei of 1×1010 cm?3 or higher. A width of a no-oxygen-precipitation-nucleus-forming-region 15, formed between the silicon epitaxial layer 2 and the silicon single substrate 1, is in the range of more than 0 ?m and less than 10 ?m. Thereby, provided is a silicon epitaxial wafer using a boron doped p+ CZ substrate, wherein a formed width of no-oxygen-precipitation-nucleus-forming-region is reduced sufficiently, and oxygen precipitates can be formed having a density sufficient enough to exert an IG effect.
    Type: Application
    Filed: July 5, 2005
    Publication date: February 14, 2008
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventors: Fumitaka Kume, Tomosuke Yushida, Ken Aihara, Ryoji Hoshi, Satoshi Tobe, Naohisa Toda, Fumio Tahara
  • Publication number: 20070269338
    Abstract: A silicon epitaxial wafer 100 is formed by growing a silicon epitaxial layer 2 on a silicon single crystal substrate 1, produced by means of a CZ method, and doped with boron so that a resistivity thereof is less than 0.018 ?·cm. The silicon single crystal substrate 1 has a density of bulk stacking faults 13 in the silicon single crystal substrate 1 in the range of 1×108 cm?3 or higher and 3×109 cm?3 or lower. Thereby, provided is a silicon epitaxial wafer having a boron doped p+ CZ substrate with a resistivity of 0.018?·cm or lower, and a state of formation of oxygen precipitates can be adjusted adequately so as to secure a sufficient IG effect and to suppress a problem of bow and deformation of a substrate, despite that sizes of oxygen precipitates is so small to be observed accurately.
    Type: Application
    Filed: June 27, 2005
    Publication date: November 22, 2007
    Applicant: Shin-Etsu Handotai Co., Ltd
    Inventors: Fumitaka Kume, Tomosuke Yoshida, Ken Aihara, Ryoji Hoshi, Satoshi Tobe, Naohisa Toda, Fumio Tahara
  • Publication number: 20070243699
    Abstract: A silicon epitaxial layer 2 is grown in vapor phase on a silicon single crystal substrate 1 manufactured by the Czochralski method, and doped with boron so as to adjust the resistivity to 0.02 ?·cm or below, oxygen precipitation nuclei 11 are formed in the silicon single crystal substrate 1, by carrying out annealing at 450° C. to 750° C., in an oxidizing atmosphere, for a duration of time allowing formation of a silicon oxide film only to as thick as 2 nm or below on the silicon epitaxial layer 2 as a result of the annealing, and thus-formed silicon oxide film 3 is etched as the first cleaning after the low-temperature annealing, using a cleaning solution. By this process, the final residual thickness of the silicon oxide film can be suppressed only to a level equivalent to native oxide film, without relying upon the hydrofluoric acid cleaning.
    Type: Application
    Filed: August 3, 2005
    Publication date: October 18, 2007
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventors: Fumitaka Kume, Tomosuke Yoshida, Ken Aihara, Ryoji Hoshi, Satoshi Tobe, Naohisa Toda, Fumio Tahara
  • Patent number: 7081422
    Abstract: There are provided a heat-treating method capable of suppressing generation of slip in a CZ silicon single crystal wafer having a diameter of mainly 300 mm or more even under high temperature heat treatment to annihilate grown-in defects in the vicinity of a surface of the wafer, and an annealed wafer having a DZ layer in a surface layer of the wafer and oxide precipitates in the bulk thereof at a high density which exert a high gettering effect. First heat treatment of a silicon single crystal wafer manufactured from a silicon single crystal ingot pulled by means of a Czochralski method is performed at a temperature in the range of 600 to 1100° C. to form oxide precipitates in the bulk of the wafer, and thereafter, second heat treatment is performed at a temperature in the range of 1150 to 1300° C.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: July 25, 2006
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yoshinori Hayamizu, Satoshi Tobe, Norihiro Kobayashi
  • Patent number: 7078357
    Abstract: There are provided a heat-treating method capable of both increasing BMD density and widening DZ layer width, and a silicon wafer having DZ layer width wider compared with a conventional one regardless of high BMD density. In the method, heat treatment (RTA treatment) is performed to a silicon wafer containing interstitial oxygen with a rapid heating-rapid cooling apparatus, thereby atomic vacancies being injected from a surface of the wafer to form a maximum position of an atomic vacancy concentration in a depth direction in the vicinity of the surface of the wafer, and thereafter heat treatment (post annealing) is performed to move the maximum position of the atomic vacancy concentration in the vicinity of the surface of the wafer into the inside of the wafer.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: July 18, 2006
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Satoshi Tobe, Ken Aihara
  • Patent number: 7071079
    Abstract: The present invention provides an epitaxial wafer wherein a silicon epitaxial layer is formed on a surface of a silicon single crystal wafer in which nitrogen is doped, and a density of oxide precipitates having such a size that a gettering capability can be achieved in a bulk is 108 numbers/cm3 or more. And the present invention also provides a method for producing an epitaxial wafer wherein a silicon single crystal in which nitrogen is doped is pulled by Czochralski method, the silicon single crystal is processed into a wafer to produce a silicon single crystal wafer, and the silicon single crystal wafer is subjected to heat treatment so that a density of oxide precipitates having such a size that a gettering capability can be achieved in a bulk of the wafer may be 108 numbers/cm3 or more, and then the silicon single crystal wafer is subjected to epitaxial growth. A silicon single crystal wafer which surely has a high gettering capability irrespective of a device process can be obtained herewith.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: July 4, 2006
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Satoshi Tobe
  • Publication number: 20060121291
    Abstract: There are provided a heat-treating method capable of suppressing generation of slip in a CZ silicon single crystal wafer having a diameter of mainly 300 mm or more even under high temperature heat treatment to annihilate grown-in defects in the vicinity of a surface of the wafer, and an annealed wafer having a DZ layer in a surface layer of the wafer and oxide precipitates in the bulk thereof at a high density which exert a high gettering effect. First heat treatment of a silicon single crystal wafer manufactured from a silicon single crystal ingot pulled by means of a Czochralski method is performed at a temperature in the range of 600 to 1100° C. to form oxide precipitates in the bulk of the wafer, and thereafter, second heat treatment is performed at a temperature in the range of 1150 to 1300° C.
    Type: Application
    Filed: November 3, 2005
    Publication date: June 8, 2006
    Inventors: Yoshinori Hayamizu, Satoshi Tobe, Norihiro Kobayashi
  • Publication number: 20040180505
    Abstract: The present invention provides an epitaxial wafer wherein a silicon epitaxial layer is formed on a surface of a silicon single crystal wafer in which nitrogen is doped, and a density of oxide precipitates having such a size that a gettering capability can be achieved in a bulk is 108 numbers/cm3 or more. And the present invention also provides a method for producing an epitaxial wafer wherein a silicon single crystal in which nitrogen is doped is pulled by Czochralski method, the silicon single crystal is processed into a wafer to produce a silicon single crystal wafer, and the silicon single crystal wafer is subjected to heat treatment so that a density of oxide precipitates having such a size that a gettering capability can be achieved in a bulk of the wafer may be 108 numbers/cm3 or more, and then the silicon single crystal wafer is subjected to epitaxial growth. A silicon single crystal wafer which surely has a high gettering capability irrespective of a device process can be obtained herewith.
    Type: Application
    Filed: February 18, 2004
    Publication date: September 16, 2004
    Inventor: Satoshi Tobe
  • Publication number: 20040102056
    Abstract: There are provided a heat-treating method capable of both increasing BMD density and widening DZ layer width, and a silicon wafer having DZ layer width wider compared with a conventional one regardless of high BMD density. In the method, heat treatment (RTA treatment) is performed to a silicon wafer containing interstitial oxygen with a rapid heating-rapid cooling apparatus, thereby atomic vacancies being injected from a surface of the wafer to form a maximum position of an atomic vacancy concentration in a depth direction in the vicinity of the surface of the wafer, and thereafter heat treatment (post annealing) is performed to move the maximum position of the atomic vacancy concentration in the vicinity of the surface of the wafer into the inside of the wafer.
    Type: Application
    Filed: April 25, 2003
    Publication date: May 27, 2004
    Inventors: Satoshi Tobe, Ken Aihara
  • Publication number: 20030013321
    Abstract: There are provided a heat-treating method capable of suppressing generation of slip in a CZ silicon single crystal wafer having a diameter of mainly 300 mm or more even under high temperature heat treatment to annihilate grown-in defects in the vicinity of a surface of the wafer, and an annealed wafer having a DZ layer in a surface layer of the wafer and oxide precipitates in the bulk thereof at a high density which exert a high gettering effect. First heat treatment of a silicon single crystal wafer manufactured from a silicon single crystal ingot pulled by means of a Czochralski method is performed at a temperature in the range of 600 to 1100° C. to form oxide precipitates in the bulk of the wafer, and thereafter, second heat treatment is performed at a temperature in the range of 1150 to 1300° C.
    Type: Application
    Filed: August 28, 2002
    Publication date: January 16, 2003
    Inventors: Yoshinori Hayamizu, Satoshi Tobe, Norihiro Kobayashi