Patents by Inventor Satoshi Tsukiyama

Satoshi Tsukiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240274442
    Abstract: A semiconductor device includes a substrate, a first adhesive layer, a first semiconductor chip, and a second adhesive layer. The first adhesive layer is provided above a first surface of the substrate and includes a plurality of types of resins having different molecular weights and a filler. The first semiconductor chip is provided above the first adhesive layer. The second adhesive layer is provided in at least a part of a first region between the substrate and the first adhesive layer, and the second adhesive layer includes at least one type of resins among the plurality of types of resins having a molecular weight smaller than a molecular weight of other types of resins among the plurality of types of resins, and a filler having a lower concentration than that of the first adhesive layer.
    Type: Application
    Filed: April 26, 2024
    Publication date: August 15, 2024
    Applicant: Kioxia Corporation
    Inventors: Satoshi TSUKIYAMA, Satoru TAKAKU, Yuki SUGO, Ayana AMANO
  • Publication number: 20240203927
    Abstract: According to one embodiment, a semiconductor device includes a wiring substrate with a first conductor portion and a second conductor portion on a first surface. A protective film is on the first surface of the wiring substrate. The protective film has a first opening exposing the first conductor portion and a second opening exposing the second conductor portion. A first electronic component is mounted to the wiring substrate. An electrode terminal of the first electronic component is connected to the first conductor portion through the first opening. A second electronic component is stacked on the first electronic component via an adhesive layer. A first resin layer is between the protective film and the first electronic component. A second resin layer is between the protective film and the adhesive layer, the second resin layer being outside the first electronic component in a plan view.
    Type: Application
    Filed: December 12, 2023
    Publication date: June 20, 2024
    Inventors: Satoshi TSUKIYAMA, Satoru TAKAKU
  • Patent number: 12002686
    Abstract: A semiconductor device includes a substrate, a first adhesive layer, a first semiconductor chip, and a second adhesive layer. The first adhesive layer is provided above a first surface of the substrate and includes a plurality of types of resins having different molecular weights and a filler. The first semiconductor chip is provided above the first adhesive layer. The second adhesive layer is provided in at least a part of a first region between the substrate and the first adhesive layer, and the second adhesive layer includes at least one type of resins among the plurality of types of resins having a molecular weight smaller than a molecular weight of other types of resins among the plurality of types of resins, and a filler having a lower concentration than that of the first adhesive layer.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: June 4, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Satoshi Tsukiyama, Satoru Takaku, Yuki Sugo, Ayana Amano
  • Publication number: 20230076668
    Abstract: A method for manufacturing a semiconductor device of an embodiment, comprises a step of mounting a first semiconductor element on a board and a step of accommodating a member in which a plate-shaped member and a first adhesive layer are stacked in a collet and pressure-bonding the heated first adhesive layer on the board on which the first semiconductor element is mounted. The collet has a member having the first Young's modulus and a second member having a second Young's modulus which is lower than the first Young's modulus on a surface that accommodates the member in which the plate-shaped member and the first adhesive layer are stacked.
    Type: Application
    Filed: March 9, 2022
    Publication date: March 9, 2023
    Applicant: Kioxia Corporation
    Inventors: Satoshi TSUKIYAMA, Hideo AOKI, Tsukasa KONNO
  • Publication number: 20230058480
    Abstract: A semiconductor device according to the present embodiment includes a substrate and a semiconductor chip. The substrate has a first face and a plurality of conductive connection parts provided on the first face. The semiconductor chip has a second face that faces the first face and a plurality of connection bumps provided on the second face and electrically connected to the plurality of conductive connection parts. The conductive connection part arranged in a chip outer peripheral region of a chip region on the first face where the semiconductor chip is arranged is different in thickness from the conductive connection part arranged in a chip central region of the chip region.
    Type: Application
    Filed: March 10, 2022
    Publication date: February 23, 2023
    Applicant: Kioxia Corporation
    Inventors: Satoshi TSUKIYAMA, Hideo AOKI, Hiroshi OOTA, Tomoyasu YAMADA, Yuki TAKAHASHI
  • Publication number: 20220246516
    Abstract: A semiconductor device according to an embodiment includes a substrate and a semiconductor chip. The semiconductor chip is provided over the substrate. The substrate includes a wire layer and an insulating layer. The wire layer includes a wire electrically connected to the semiconductor chip. The insulating layer is provided in contact with the wire layer and includes a glass woven fabric containing a resin. The glass woven fabric includes a plurality of glass fibers that are provided along two or more directions parallel with the glass woven fabric and are woven. The glass fibers differ in at least one of the material, number, and thickness depending on the directions parallel with the glass woven fabric.
    Type: Application
    Filed: August 30, 2021
    Publication date: August 4, 2022
    Applicant: Kioxia Corporation
    Inventors: Hideo AOKI, Hideko MUKAIDA, Satoshi TSUKIYAMA
  • Patent number: 11270981
    Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: March 8, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Mikihiko Ito, Masaru Koyanagi, Masafumi Nakatani, Shinya Okuno, Shigeki Nagasaka, Masahiro Yoshihara, Akira Umezawa, Satoshi Tsukiyama, Kazushige Kawasaki
  • Publication number: 20210233781
    Abstract: A semiconductor device includes a substrate, a first adhesive layer, a first semiconductor chip, and a second adhesive layer. The first adhesive layer is provided above a first surface of the substrate and includes a plurality of types of resins having different molecular weights and a filler. The first semiconductor chip is provided above the first adhesive layer. The second adhesive layer is provided in at least a part of a first region between the substrate and the first adhesive layer, and the second adhesive layer includes at least one type of resins among the plurality of types of resins having a molecular weight smaller than a molecular weight of other types of resins among the plurality of types of resins, and a filler having a lower concentration than that of the first adhesive layer.
    Type: Application
    Filed: August 27, 2020
    Publication date: July 29, 2021
    Applicant: KIOXIA CORPORATION
    Inventors: Satoshi TSUKIYAMA, Satoru TAKAKU, Yuki SUGO, Ayana AMANO
  • Patent number: 10943844
    Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip thicker than the first semiconductor chip, a plurality of bumps provided between the first and second semiconductor chips and electrically connecting the first and second semiconductor chips, an adhesive resin provided between the first and second semiconductor chips and bonding the first and second semiconductor chips, and a sealing resin encapsulating the first and second semiconductor chips. At least one of the first and second semiconductor chips has an organic protective film disposed thereon.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Hideo Aoki, Masatoshi Kawato, Masayuki Miura, Masatoshi Fukuda, Soichi Homma
  • Patent number: 10892251
    Abstract: According to one embodiment, a semiconductor device includes a wiring board, a controller chip that is provided on the wiring board and is sealed with a first resin composition, a nonvolatile memory chip that is provided on the first resin composition and is sealed with a second resin composition, a second bonding wire that connects a pad for electric power supply wiring of the controller chip to the wiring board and is sealed with the first resin composition, and a first bonding wire that connects a pad for signal wiring of the controller chip to the wiring board, is sealed with the first resin composition, and has a higher Pd content than that of the second bonding wire.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: January 12, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Hideo Aoki
  • Publication number: 20210005580
    Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.
    Type: Application
    Filed: September 17, 2020
    Publication date: January 7, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Mikihiko ITO, Masaru KOYANAGI, Masafumi NAKATANI, Shinya OKUNO, Shigeki NAGASAKA, Masahiro YOSHIHARA, Akira UMEZAWA, Satoshi TSUKIYAMA, Kazushige KAWASAKI
  • Patent number: 10811393
    Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: October 20, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Mikihiko Ito, Masaru Koyanagi, Masafumi Nakatani, Shinya Okuno, Shigeki Nagasaka, Masahiro Yoshihara, Akira Umezawa, Satoshi Tsukiyama, Kazushige Kawasaki
  • Publication number: 20200303346
    Abstract: According to one embodiment, a semiconductor device includes a wiring board, a controller chip that is provided on the wiring board and is sealed with a first resin composition, a nonvolatile memory chip that is provided on the first resin composition and is sealed with a second resin composition, a second bonding wire that connects a pad for electric power supply wiring of the controller chip to the wiring board and is sealed with the first resin composition, and a first bonding wire that connects a pad for signal wiring of the controller chip to the wiring board, is sealed with the first resin composition, and has a higher Pd content than that of the second bonding wire.
    Type: Application
    Filed: September 3, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi TSUKIYAMA, Hideo AOKI
  • Patent number: 10734360
    Abstract: A semiconductor device includes a base member and semiconductor chips stacked on the base member. The semiconductor chips include a first semiconductor chip and a second semiconductor chip adjacent to the first semiconductor chip. The first semiconductor chip includes a semiconductor substrate, a functional layer and through electrodes. The through electrodes extend from the back surface to the front surface of the semiconductor substrate, and are electrically connected to the functional layer on the front surface. The second semiconductor chip is electrically connected to the first semiconductor chip through connection members connected to the through electrodes. The functional layer includes first and second contact pads. The second contact pad is positioned at a level between the semiconductor substrate and the first contact pad. The through electrodes include a first through electrode connected to the first contact pad and a second through electrode connected to the second contact pad.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: August 4, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Masaru Koyanagi, Mikihiko Ito, Kazushige Kawasaki
  • Patent number: 10707193
    Abstract: According to one embodiment, a semiconductor device of an embodiment includes a substrate, a metal plate having a main portion having a first width in a first direction and a second width in a second direction orthogonal to the first direction, a first semiconductor chip located between the metal plate and the substrate, the first semiconductor chip having a third width in the first direction and a fourth width in the second direction, and a second semiconductor chip located between the first semiconductor chip and the substrate, wherein the first width is smaller than the third width, and the second width is smaller than the fourth width.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: July 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Hideo Aoki, Yoshiaki Goto
  • Patent number: 10707174
    Abstract: According to one embodiment, a semiconductor device includes a device region covered with a resin film and a dicing region extending along at least one side of the device region, the dicing region including at least a first lithography mark and a second lithography mark. The resin film includes a first dicing region portion which covers a portion of the dicing region between the first lithography mark and the second lithography mark.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: July 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Hideo Aoki
  • Patent number: 10593649
    Abstract: A semiconductor device includes a base member, a stacked body on the base member, a first conductor on the stacked body, a second conductor on a top surface of the base member, and a connection conductor connecting the first conductor and the second conductor. The stacked body includes semiconductor chips stacked and a shared terminal connected to the plurality of semiconductor chips. The plurality of semiconductor chips each includes a functional element on a front surface side thereof and a through electrode extending from a back surface to the front surface side. The shared terminal has a top end positioned at a top surface of the stacked body and a bottom end positioned at a bottom surface of the stacked body. The first conductor is connected to the top end of the shared terminal, and the second conductor is electrically connected to the bottom end of the shared terminal.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: March 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Masaru Koyanagi, Mikihiko Ito, Kazushige Kawasaki
  • Publication number: 20190393114
    Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip thicker than the first semiconductor chip, a plurality of bumps provided between the first and second semiconductor chips and electrically connecting the first and second semiconductor chips, an adhesive resin provided between the first and second semiconductor chips and bonding the first and second semiconductor chips, and a sealing resin encapsulating the first and second semiconductor chips. At least one of the first and second semiconductor chips has an organic protective film disposed thereon.
    Type: Application
    Filed: February 5, 2019
    Publication date: December 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Satoshi TSUKIYAMA, Hideo AOKI, Masatoshi KAWATO, Masayuki MIURA, Masatoshi FUKUDA, Soichi HOMMA
  • Patent number: 10497688
    Abstract: A semiconductor device according to an embodiment includes a first memory chip having a first front surface and a first back surface and having a first memory circuit provided on the first front surface side; a second memory chip having a second front surface and a second back surface facing the first front surface, having a second memory circuit provided on the second front surface side, and being electrically connected to the first memory chip; and a logic chip having the first memory chip provided between the logic chip and the second memory chip, having a third front surface and a third back surface, having a logic circuit provided on the third front surface side, and being electrically connected to the first memory chip.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: December 3, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Tsukiyama, Yoichiro Kurita, Hideo Aoki, Kazushige Kawasaki
  • Publication number: 20190295987
    Abstract: A semiconductor device includes a base member, a stacked body on the base member, a first conductor on the stacked body, a second conductor on a top surface of the base member, and a connection conductor connecting the first conductor and the second conductor. The stacked body includes semiconductor chips stacked and a shared terminal connected to the plurality of semiconductor chips. The plurality of semiconductor chips each includes a functional element on a front surface side thereof and a through electrode extending from a back surface to the front surface side. The shared terminal has a top end positioned at a top surface of the stacked body and a bottom end positioned at a bottom surface of the stacked body. The first conductor is connected to the top end of the shared terminal, and the second conductor is electrically connected to the bottom end of the shared terminal.
    Type: Application
    Filed: September 4, 2018
    Publication date: September 26, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Masaru Koyanagi, Mikihiko Ito, Kazushige Kawasaki