Patents by Inventor Satoshi Uchiya

Satoshi Uchiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090206372
    Abstract: A solid-state imaging device includes an N-type semiconductor substrate, an N-type impurity region provided in the surficial portion of the N-type semiconductor substrate, a photo-electric conversion unit formed in the N-type impurity region, a charge accumulation unit formed in the N-type impurity region so as to contact with the photo-electric conversion unit, and temporarily accumulating charge generated in the photo-electric conversion unit, a charge hold region (barrier unit) formed in the N-type impurity region so as to contact with the charge accumulation unit, and allowing the charge accumulation unit to accumulate the charge, and a charge accumulating electrode provided to the charge accumulation unit. The charge accumulation unit and the charge hold region are formed to be N?-type.
    Type: Application
    Filed: February 25, 2009
    Publication date: August 20, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Hiroyoshi KUDOU, Satoshi UCHIYA, Junichi YAMAMOTO, Fumiaki FATAMURA
  • Patent number: 7547976
    Abstract: A pad structure 100 includes an electrode pad (a first electrically conducting film 104 and a second electrically conducting film 110) and an insulating film provided over a peripheral region of the electrode pad so as to surround the electrode pad, and the insulating film has a structure including a protective film (a cover oxide film 106) and a transparent resin film (a transparent resin 108) provided on the cover oxide film 106.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: June 16, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Taro Moriya, Yasutaka Nakashiba, Satoshi Uchiya, Masayuki Furumiya
  • Patent number: 7514729
    Abstract: A solid-state imaging device includes an N-type semiconductor substrate, an N-type impurity region provided in the surficial portion of the N-type semiconductor substrate, a photo-electric conversion unit formed in the N-type impurity region, a charge accumulation unit formed in the N-type impurity region so as to contact with the photo-electric conversion unit, and temporarily accumulating charge generated in the photo-electric conversion unit, a charge hold region (barrier unit) formed in the N-type impurity region so as to contact with the charge accumulation unit, and allowing the charge accumulation unit to accumulate the charge, and a charge accumulating electrode provided to the charge accumulation unit. The charge accumulation unit and the charge hold region are formed to be N?-type.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: April 7, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Hiroyoshi Kudou, Satoshi Uchiya, Junichi Yamamoto, Fumiaki Futamura
  • Publication number: 20070096159
    Abstract: A solid-state imaging device includes an N-type semiconductor substrate, an N-type impurity region provided in the surficial portion of the N-type semiconductor substrate, a photo-electric conversion unit formed in the N-type impurity region, a charge accumulation unit formed in the N-type impurity region so as to contact with the photo-electric conversion unit, and temporarily accumulating charge generated in the photo-electric conversion unit, a charge hold region (barrier unit) formed in the N-type impurity region so as to contact with the charge accumulation unit, and allowing the charge accumulation unit to accumulate the charge, and a charge accumulating electrode provided to the charge accumulation unit. The charge accumulation unit and the charge hold region are formed to be N?-type.
    Type: Application
    Filed: September 12, 2006
    Publication date: May 3, 2007
    Applicant: NEC Electronics Corporation
    Inventors: Hiroyoshi Kudou, Satoshi Uchiya, Junichi Yamamoto, Fumiaki Futamura
  • Publication number: 20060073628
    Abstract: The invention reduces dark current of a solid-state imaging device. A solid-state imaging device containing photodiode comprises: a diffusion layer placed side by side with the photodiode on the surface of an N-type semiconductor substrate; a first polycrystalline silicon electrode provided on the diffusion layer; a first Al interconnect provided on the first polycrystalline silicon electrode; a contact plug connecting the lower surface of the first Al interconnect and the first polycrystalline silicon electrode; and an adhesive film that is a titanium-containing film selectively provided within the contact plug.
    Type: Application
    Filed: October 3, 2005
    Publication date: April 6, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Satoshi Uchiya, Taro Moriya, Junichi Yamamoto
  • Publication number: 20050242433
    Abstract: A pad structure 100 includes an electrode pad (a first electrically conducting film 104 and a second electrically conducting film 110) and an insulating film provided over a peripheral region of the electrode pad so as to surround the electrode pad, and the insulating film has a structure including a protective film (a cover oxide film 106) and a transparent resin film (a transparent resin 108) provided on the cover oxide film 106.
    Type: Application
    Filed: May 2, 2005
    Publication date: November 3, 2005
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Taro Moriya, Yasutaka Nakashiba, Satoshi Uchiya, Masayuki Furumiya
  • Patent number: 6194242
    Abstract: A solid-state imaging device that prevents the transfer errors of the signal charges from vertical charge-transfer sections to a horizontal charge-transfer section. A first plurality of buried channel regions in vertical charge-transfer sections are connected to a second buried channel region in a horizontal charge-transfer section so that the interfaces between the first plurality of buried channel regions and the second buried channel region are located to be aligned with the corresponding ends of the first plurality of gate electrodes. Thus, no potential dip nor potential barrier are generated in the vicinity of the interfaces between the first plurality of buried channel regions and the second buried channel region.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: February 27, 2001
    Assignee: NEC Corporation
    Inventor: Satoshi Uchiya
  • Patent number: 6114717
    Abstract: A solid-state imaging device that prevents the transfer errors of the signal charges from vertical charge-transfer sections to a horizontal charge-transfer section. A first plurality of buried channel regions in vertical charge-transfer sections are connected to a second buried channel region in a horizontal charge-transfer section so that the interfaces between the first plurality of buried channel regions and the second buried channel region are located to be aligned with the corresponding ends of the first plurality of gate electrodes. Thus, no potential dip nor potential barrier are generated in the vicinity of the interfaces between the first plurality of buried channel regions and the second buried channel region.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: September 5, 2000
    Assignee: NEC Corporation
    Inventor: Satoshi Uchiya
  • Patent number: 5567632
    Abstract: A solid state image sensor device includes: a photoelectric conversion section having a first conductivity type semiconductor thin region and a second conductivity type semiconductor region in a surface area of a first conductivity type semiconductor layer; a signal electron transfer section formed within the surface area of the first conductivity type semiconductor layer, for transferring a signal electron generated at the photoelectric conversion section; and a signal electron read-out section formed over the surface area of the first conductivity type semiconductor layer, for reading-out the signal electron from the photoelectric conversion section to the signal electron transfer section. The first conductivity type semiconductor thin region is self-aligned with respect to the second conductivity type semiconductor region and this is achieved by using the same mask and controlling the angles of incidence in the ion implantation.
    Type: Grant
    Filed: October 18, 1993
    Date of Patent: October 22, 1996
    Inventors: Yasutaka Nakashiba, Satoshi Uchiya
  • Patent number: 5258608
    Abstract: A solid-state color imaging device comprises a semiconductor substrate having a plurality of optoelectrical conversion regions on a major surface of the substrate and an insulating layer on the major surface of the substrate. On the insulating layer is a light shielding layer having an array of holes respectively aligned with the optoelectrical conversion regions. On the light shielding layer is an anti-reflection layer to absorb light reflected from the light shielding layer. A color anti-blending layer and a color dyeing layer are successively formed on the anti-reflection layer. The color dyeing layer has an array of color filtering regions in positions which correspond respectively to the optoelectrical conversion regions.
    Type: Grant
    Filed: November 29, 1991
    Date of Patent: November 2, 1993
    Assignee: NEC Corporation
    Inventor: Satoshi Uchiya