Patents by Inventor Satoshi UETAKE

Satoshi UETAKE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Vehicle
    Patent number: 12576293
    Abstract: A vehicle includes a battery, a battery case accommodating the battery, and a propeller shaft extending in a front-rear direction of the vehicle. The propeller shaft is covered by a propeller shaft case. An internal space of the propeller shaft case communicates with an internal space of the battery case. The vehicle is provided with at least one fire extinguishing hole communicating with the internal space of the propeller shaft case.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: March 17, 2026
    Assignee: SUBARU CORPORATION
    Inventors: Yoshinobu Yamazaki, Satoshi Uetake, Hisae Sawada, Yuya Aoki, Tokito Kobayashi, Toshiaki Naruke
  • VEHICLE
    Publication number: 20250025725
    Abstract: A vehicle includes a battery, a battery case accommodating the battery, and a propeller shaft extending in a front-rear direction of the vehicle. The propeller shaft is covered by a propeller shaft case. An internal space of the propeller shaft case communicates with an internal space of the battery case. The vehicle is provided with at least one fire extinguishing hole communicating with the internal space of the propeller shaft case.
    Type: Application
    Filed: September 22, 2022
    Publication date: January 23, 2025
    Inventors: Yoshinobu YAMAZAKI, Satoshi UETAKE, Hisae SAWADA, Yuya AOKI, Tokito KOBAYASHI, Toshiaki NARUKE
  • Semiconductor device, test method thereof, and system
    Patent number: 9330786
    Abstract: A semiconductor device includes a plurality of chips comprising a plurality of I/O terminals connected in common via through electrodes. Each of the chips includes an I/O compression circuit operable to output a compression result obtained by compression of data of a plurality of internal data buses to a first I/O terminal of the plurality of I/O terminals. Each of the chips also includes a test control circuit having a register group that sets the number of the first I/O terminal. Setting information that assigns different first I/O terminals to different chips is set in the register group. Each of the chips inputs or outputs data with use of the number of the I/O terminal that is different from those in other chips. Thus, the I/O compression circuits can concurrently perform an I/O compression test in parallel in the plurality of chips without a bus fight.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: May 3, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Satoshi Uetake, Yuji Uo
  • SEMICONDUCTOR DEVICE, TEST METHOD THEREOF, AND SYSTEM
    Publication number: 20110184688
    Abstract: A semiconductor device includes a plurality of chips comprising a plurality of I/O terminals connected in common via through electrodes. Each of the chips includes an I/O compression circuit operable to output a compression result obtained by compression of data of a plurality of internal data buses to a first I/O terminal of the plurality of I/O terminals. Each of the chips also includes a test control circuit having a register group that sets the number of the first I/O terminal. Setting information that assigns different first I/O terminals to different chips is set in the register group. Each of the chips inputs or outputs data with use of the number of the I/O terminal that is different from those in other chips. Thus, the I/O compression circuits can concurrently perform an I/O compression test in parallel in the plurality of chips without a bus fight.
    Type: Application
    Filed: January 24, 2011
    Publication date: July 28, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Satoshi UETAKE, Yuji UO