Abstract: Provided are a thin film transistor, a display device, and a thin film transistor manufacturing method, in which variation in characteristics is small. The present invention is provided with: a gate electrode formed on a substrate; a gate insulation film formed so as to cover the gate electrode; a semiconductor layer which is formed on the upper side of the gate insulation film and which includes a polysilicon layer disposed, in a plan view, inside a region defined by the gate electrode; an etching stopper layer disposed on the upper side of the polysilicon layer; and a source electrode and a drain electrode provided on the semiconductor layer so as to be separated from each other, wherein the polysilicon layer has first and second regions which are not covered with the etching stopper layer, and a part of the source electrode exists above the first region and a part of the drain electrode exists above the second region.

Abstract: A semiconductor storage unit is provided with a memory cell array that is sectioned into a plurality of blocks, a redundant memory cell, and a redundant memory cell selection circuit for replacing a defective cell in the memory cell array with the redundant memory cell. The redundant memory cell selection circuit is provided with n-channel MOS transistors (N00-N03) to whose gates a block selection signal (BLK) is input, p-channel MOS transistors (P0-P3) to whose gates a block selection signal (BLKB) that is reverse in logical value to the block selection signal (BLK) is input, and fuses (F0-F3) that are connected between the sources or drains of the transistors (N00-N03) and those of the transistors (P0-P3), respectively. Thereby, it is possible to reduce the number of fuses and the size of a chip.

Abstract: A plurality of bit line pairs are provided in a semiconductor memory device. A plurality of memory cells are connected to the first bit line pairs. Also, in the semiconductor memory device, there are provided a first sense amplifier, a second bit line pair and a second sense amplifier. The first sense amplifier reads and amplifies a potential difference between the first bit line pair. A signal output from the first sense amplifier is transmitted to the second bit line pair. The second sense amplifier amplifies a potential difference between the second bit line pair. A precharge circuit is built in the second sense amplifier. The first bit line pairs are precharged by the precharge circuit.

Abstract: In order to achieve a speed up of threshold value correcting operation and read operation of level detecting transistors of a semiconductor memory device and a reduction of an area of a chip thereof, a sense amplifier SA10 includes a threshold value correction driving transistor Q16 responsive to a threshold value correction drive signal RSB1 to correct levels of bit lines of data lines DL11 and DL12 with respect to threshold values of level detecting transistors Q11 and Q21 during a precharge period T2 and a read driving transistor Q15 responsive to a read control signal RS1 to activate the transistors Q11 and Q21 such that the latter transistors detect the levels of the bit lines of the data lines DL11 and DL12 during a read period T3.

Abstract: A semiconductor dynamic random access memory device has first open bit lines arranged in parallel and second open bit lines respectively paired with the first open bit lines so as to form bit line pairs and a sense amplifier shared between the bit line pairs so as to increase the magnitude of a potential difference indicative of a data bit sequentially supplied from the bit line pairs, and either high or low level indicative of the data bit is supplied to both first and second bit lines of the selected bit line pair upon completion of the sense amplification, thereby equalizing electric influence on the adjacent open bit lines.

Abstract: A data refresh is indispensable for a semiconductor dynamic random access memory device, and electric charges are recycled from bit line pairs for a row of memory cell arrays to power supply lines for bit line drivers associated with the next row of memory cell arrays and from bit line pairs for the next row of memory cell arrays to power supply lines for the row of memory cell arrays, thereby reducing power consumption in the data refresh.

Abstract: In a semiconductor memory device including: a plurality of sub word lines, a plurality of sub word decoders each connected to one of the sub word lines, a plurality of pairs of main word lines each pair connected to a number of the sub word decoders, and a plurality of main word decoders each connected to one of the pairs of main word lines, each of the main word decoders sets voltages at a respective pair of the pairs of main word lines different from each other in a selection mode and sets the voltages at a respective pair of the pairs of main word lines the same as each other in a non-selection mode.