Abstract: Provided is a connection structure for superconductor wires, in which two superconductor wires include respective oxide superconducting conductor layers each formed on one surface of a base material. The oxide superconducting conductor layers are conjoined with each other while facing each other at a connected end of each of the two superconductor wires. An embedment material for reinforcement is provided from one of the two superconductor wires to the other one of the two superconductor wires in a thickness direction of the two superconductor wires at the connected end of each of the two superconductor wires.

Abstract: A connection structure of the present disclosure includes first and second superconducting wires that are two superconducting wires each having a substrate in a tape shape, an intermediate layer formed on the substrate, and a superconductor layer formed on the intermediate layer, a connecting superconductor layer that connects the first and second superconducting wires in a positional relationship in which surfaces of the superconductor layers face each other, and forms a superconducting connecting section together with the first and second superconducting wires, two protective members each having a width larger than a width of the first and second superconducting wires and disposed on substrates sides of the first and second superconducting wires in a positional relationship of sandwiching the superconducting connecting section, and a metal part that joins the two protective members to each other.

Abstract: Provided is a connection structure for superconductor wires, in which two superconductor wires include respective oxide superconducting conductor layers each formed on one surface of a base material. The oxide superconducting conductor layers are conjoined with each other while facing each other at a connected end of each of the two superconductor wires. An embedment material for reinforcement is provided from one of the two superconductor wires to the other one of the two superconductor wires in a thickness direction of the two superconductor wires at the connected end of each of the two superconductor wires.

Abstract: A method for producing an insulated electric wire comprises a first step of processing a copper alloy containing a tin and inevitable impurities into a fine wire having a diameter of 0.21 mm±0.008 mm, the tin being 0.30 wt % or more and 0.39 wt % or less, a second step of annealing the fine wire obtained in the first step so as to refine the fine wire to have an extension coefficient of 10% or more and 25% or less and a tensile strength of 300 MPa or more and 400 MPa or less, and a third step of twisting the seven fine wires having undergone the second step with a twist pitch of 15 mm±6 mm.

Abstract: A heat-resistant and oil-resistant insulated electric wire is mounted on a vehicle, and includes a conductor portion and an insulator covering a periphery of the conductor portion. The insulator is made of polyphenylene sulfide resin. The conductor portion includes a twisted wire formed by twisting a plurality of element wires. At least a part of the plurality of element wires includes a plated fiber. The plated fiber is formed of a high-strength fiber and metal plating surrounding a periphery of the high-strength fiber.

Abstract: According to one embodiment, a semiconductor memory device includes a core section, a corner area adjacent section, a first circuit block and a second circuit block, and multiple wiring layers. The corner area adjacent section is arranged adjacently to a corner area positioned in a corner of the core section adjacently to the sense amplifier and the row decoder. The multiple wiring layers are provided in each of the first circuit block and the second circuit block, wherein a first wire in one of the multiple wiring layers in the first circuit block is arranged parallel to a second wire included in a wiring layer in the second circuit block which is the same as the wiring layer of the first wire.

Abstract: According to one embodiment, a semiconductor memory device includes a core section, a corner area adjacent section, a first circuit block and a second circuit block, and multiple wiring layers. The corner area adjacent section is arranged adjacently to a corner area positioned in a corner of the core section adjacently to the sense amplifier and the row decoder. The multiple wiring layers are provided in each of the first circuit block and the second circuit block, wherein a first wire in one of the multiple wiring layers in the first circuit block is arranged parallel to a second wire included in a wiring layer in the second circuit block which is the same as the wiring layer of the first wire.

Abstract: A method for producing an insulated electric wire comprises a first step of processing a copper alloy containing a tin and inevitable impurities into a fine wire having a diameter of 0.21 mm±0.008 mm, the tin being 0.30 wt % or more and 0.39 wt % or less, a second step of annealing the fine wire obtained in the first step so as to refine the fie wire to have an extension coefficient of 10% or more and 25% or less and a tensile strength of 300 MPa or more and 400 MPa or less, and a third step of twisting the seven fine wires having undergone the second step with a twist pitch of 15 mm±6 mm.

Abstract: A cold wall type CVD apparatus that can enhance a raw material yield is provided. The CVD apparatus has a raw material gas jetting unit 11 for jetting raw material gas, a susceptor 14 for supporting a tape-shaped base material T and heating the tape-shaped base material T through heat transfer, a heater 15 for heating the susceptor 14, an inert gas introducing unit 12a for introducing inert gas to suppress the contact between the heater and the raw material gas, and a raw material gas transport passage LG for guiding the raw material gas jetted from the raw material gas jetting unit 11 to the surface of the tape-shaped base material.

Abstract: A FIFO memory device using a serial pointer consists of first and second memory cell arrays, a row decoder for selecting a word line, first and second write registers for storing data, each write register consisting of registers, and a serial write pointer for serially selecting each register. The serial write pointer consists of pointers corresponding to the first and second write registers. The row decoder is located between the first memory cell array and the second memory cell array. In the device, in adjacent registers in each write register, the shift direction of one register indicated by said serial write pointer is opposed to the shift direction of the other register.

Abstract: A FIFO memory device using a serial pointer consists of first second memory cell arrays, a row decoder for selecting a word line first and second write registers for storing data, each write register consisting of registers, and a serial write pointer for serially selecting each register. The serial write pointer consists of pointers corresponding to the first and second write registers. The row decoder is located between the first memory cell array and the second memory cell array. In the device, in adjacent registers in each write register, the shift direction of one register indicated by said serial write pointer is opposed to the shift direction of the other register.

Abstract: A semiconductor device is provided with a first protection path between a first terminal and an input terminal, a second protection path between a second power source terminal and the input terminal, and a third protection path between the first and the second power source terminals. Each protection path includes a first and a second P-N junction formed to be reverse biased, and is made conductive when the voltage between the corresponding two terminals exceeds a predetermined voltage so as to protect an internal circuit connected to the input terminal from an electrostatic breakdown.