Abstract: In a vertical field effect transistor having a trench gate and a method of manufacturing the same according to the present invention, p-type base and n.sup.+ -type source diffusion layers are formed in this order in a surface region of an n.sup.31 -type epitaxial layer on an n.sup.+ -type semiconductor substrate. A trench is then provided to such a depth as to penetrate the diffusion layers. A dope polysilicon layer is deposited and buried into the trench with a gate insulation film interposed between them. The polysilicon layer is etched to have the same level as that of the entrance of the trench, and a dope polysilicon layer 18 is selectively grown thereon, thereby forming a trench gate in which an upper corner portion of the trench is not covered with a gate electrode. Consequently, the concentration of electric fields at the corner portion can be mitigated thereby to increase an absolute withstand voltage of the gate and the variations in threshold voltage can be suppressed in a BT test.

Abstract: In a vertical power MOSFET having a U-shaped trench gate and a method of manufacturing the same, a P-type base layer and an N.sup.+ -type emitter layer are formed on the surface of an N-type semiconductor substrate. A plurality of trenches are formed to such a depth as to reach the semiconductor substrate. After that, an oxide film and a nitride film are formed in this order on the surface of the resultant element and on the inner surfaces of the trenches. In this case, the oxide film and nitride film are each formed to have a thickness corresponding to the operating characteristics of the element at the stage of design. The nitride film of a gate wiring region is selectively removed to form an oxide film on the surface of the element. Consequently, a thick gate insulation film of the oxide films can be formed between the corner portions of the N.sup.

Abstract: In a vertical power MOSFET having a U-shaped trench gate and a method of manufacturing the same, a P-type base layer and an N.sup.+ -type emitter layer are formed on the surface of an N-type semiconductor substrate. A plurality of trenches are formed to such a depth as to reach the semiconductor substrate. After that, an oxide film and a nitride film are formed in this order on the surface of the resultant element and on the inner surfaces of the trenches. In this case, the oxide film and nitride film are each formed to have a thickness corresponding to the operating characteristics of the element at the stage of design. The nitride film of a gate wiring region is selectively removed to form an oxide film on the surface of the element. Consequently, a thick gate insulation film of the oxide films can be formed between the corner portions of the N.sup.

Abstract: A chemical vapor deposition apparatus comprises a reaction chamber for annealing a silicon wafer, a transportation mechanism for transporting the silicon wafer to the reaction chamber, a detecting device for detecting temperature of the reaction chamber, and an operation control device for receiving signals corresponding to the temperature of the reaction chamber, and supplying to the transportation mechanism, other signals for preventing the silicon wafer from being transported when the temperature is 100.degree. C. or more.

Abstract: A channel region and a source region are formed on a surface of a substrate by double diffusion. A trench is formed so as to penetrate a part of the channel region and a part of the source region and reach the substrate. After an insulating film is formed on an inner wall of the trench, a polysilicon layer is buried up to an intermediate portion of the trench. In this state, channel ions are implanted in a side surface region of the trench, thereby depleting a channel region. Thereafter, a polysilicon layer for leading out a gate is buried in the trench.

Abstract: A vertical MOSFET includes a trench whose inner surface is covered with an insulating layer having a multilayer structure. In order to reduce a change in a gate threshold voltage, and equivalent silicon dioxide thickness of the gate insulating layer and a radius of curvature of an upper corner of the trench are provided such that a dielectric breakdown electric field strength of the gate insulating layer at the upper corner is in the range of 2.5 MV/cm to 5.0 MV/cm.

Abstract: A vertical MOS transistor comprises a semiconductor substrate, a first impurity region defined on the surface of the semiconductor substrate, a second impurity region defined under the first impurity region, the conduction type of the second impurity region being opposite to that of the first impurity region, a trench engraved on the surface of the semiconductor substrate to cut through the first and second impurity regions deeper than at least the bottom of the second impurity region, and a gate electrode disposed in the trench with a gate insulation film interposing between the wall of the trench and the gate electrode. The gate insulation film is thicker on the bottom of the trench and on part of the side walls of the trench continuous to the bottom than on the other parts.

Abstract: A vertical MOS transistor comprises a semiconductor substrate, a first impurity region defined on the surface of the semiconductor substrate, a second impurity region defined under the first impurity region, the conduction type of the second impurity region being opposite to that of the first impurity region, a trench engraved on the surface of the semiconductor substrate to cut through the first and second impurity regions deeper than at least the bottom of the second impurity region, and a gate electrode disposed in the trench with a gate insulation film interposing between the wall of the trench and the gate electrode. THE gate insulation film is thicker on the bottom of the trench and on part of the side walls of the trench continuous to the bottom than on the other parts.

Abstract: For controlling unwanted production of crystal defects from corners of isolated regions in a complete dielectric isolation structure, after at least one trench or groove is provided through a mask of an insulating film in a semiconductor substrate adhered to an insulating film of a base substrate, the mask is side-etched and the insulating film of the base substrate is selectively etched at the same time to expose corners of the semiconductor substrate. The exposed corners of the semiconductor substrate is then subjected to isotropic etching to remove a pointed portion therefrom. Thereafter, side surfaces of the semiconductor substrate exposed within the trench is oxidized to provide an insulating film for dielectric isolation which has rounded corners.

Abstract: A bonded substrate comprises a first semiconductor substrate in which a plurality of semiconductor elements are formed, a second semiconductor substrate adhered to the first semiconductor substrate so as to support it by means of an insulating layer interposed therebetween, a first semi-insulating polysilicon layer interposed between the first semiconductor substrate and the insulating layer, and a second semi-insulating polysilicon layer interposed between the insulating layer and the second semiconductor substrate. The semi-insulating polysilicon layers serve to reduce the voltage applied to the insulating layer and to prevent the insulating layer from being etched.