Patents by Inventor Satoshi Yatabe

Satoshi Yatabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7148427
    Abstract: A wiring substrate is formed of a plurality of metal wirings 14e formed on a substrate 7c. A guard wiring 29 fabricated of an electrically conductive oxide such as ITO is interposed between at least a pair of adjacent ones of a plurality of metal wirings 14e. When voltages V1, V2, V3, and V4 applied to the metal wirings 14e are related to be V1>V2>V3>V4, a guard wiring 29 is present between a metal wiring 14e functioning as an anode and a metal wiring 14e functioning as a cathode, and the anode metal wiring 14e is prevented from being corroded.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: December 12, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Yasuhito Aruga, Satoshi Yatabe, Kogo Endo, Norihito Harada
  • Patent number: 7034816
    Abstract: The present invention provides a system and method for driving a display device where out of a display screen, only pixels at intersections of particular scanning lines and particular data lines are used as a display area. In order to save power, the particular scanning lines are selected one for each horizontal scanning period. For one of the two split halves of the one horizontal scanning period, the selected scanning line is supplied with a selection voltage, and the polarity of the selection voltage is inverted at least every two or more horizontal scanning periods. The scanning lines other than the particular scanning lines are supplied with a non-selection voltage, which is inverted at least every one vertical scanning period.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: April 25, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Satoshi Yatabe
  • Publication number: 20060056119
    Abstract: A voltage supply circuit includes a first holding element with a first end and a second end that supplies a voltage held between the first end and the second end to a load, the second end being connected to a ground, and a second holding element with a first end and a second end, the first end of the second holding element being electrically connected to the first end of the first holding element. The voltage supply circuit also includes a charging circuit that charges the second holding element with a voltage higher than the voltage to be supplied to the load in a first mode, and a potential adjusting circuit that shifts a potential at the second end of the second holding element towards a potential at the first end of the first holding element according to the voltage held by the first holding element or the second holding element in a second mode exclusive with respect to the first mode.
    Type: Application
    Filed: August 25, 2005
    Publication date: March 16, 2006
    Inventors: Fusashi Kimura, Satoshi Yatabe, Kenichi Tajiri
  • Publication number: 20050195542
    Abstract: A power-supply circuit includes a capacitor, which is connected to a terminal at a first end while being grounded at the second end, for supplying a hold voltage between both ends thereof to a load; a capacitor connected, via a diode, to the terminal at a first end; an operational amplifier for raising a voltage at the second end of the capacitor, in response to a reduction in the hold voltage, such that the hold voltage becomes equal to a target voltage; and a transistor.
    Type: Application
    Filed: March 1, 2005
    Publication date: September 8, 2005
    Inventors: Fusashi Kimura, Satoshi Yatabe, Kenichi Tajiri
  • Patent number: 6940484
    Abstract: This invention provides a system for driving a display device that uses only a longitudinally elongated region in a display screen as a display region, and limits the power consumption to a lower level.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: September 6, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Satoshi Yatabe
  • Publication number: 20050110731
    Abstract: An electro-optical device includes pixels provided at intersections of a plurality of scanning lines and a plurality of data lines, a scanning line driving circuit for applying a selected voltage to the respective scanning lines, and a data line driving circuit for applying a turning-on voltage or a turning-off voltage to the respective data lines.
    Type: Application
    Filed: September 24, 2004
    Publication date: May 26, 2005
    Inventors: Kenichi Tajiri, Satoshi Yatabe
  • Publication number: 20050088105
    Abstract: An electro-optical apparatus is provided which corrects a voltage applied to a pixel with high accuracy. An electro-optical apparatus includes a correction circuit. When, for example, a positive-polarity selection voltage +VS is applied to a scanning line during the second-half period of one horizontal scanning period, the correction circuit detects a spike resulting from voltage switching from a voltage ?VD/2 to a voltage +VD/2 on the data lines, determines whether the level of the detected spike is a threshold level or more, and if a determination is made that the level of the detected spike is the threshold level or more, adds a pulse with the same polarity as that of the detected spike to a selection-voltage supply line in the second-half period following the first-half period.
    Type: Application
    Filed: September 1, 2004
    Publication date: April 28, 2005
    Inventors: Kenichi Tajiri, Satoshi Yatabe
  • Patent number: 6822631
    Abstract: In order to reduce power consumption in halftone display, each horizontal scanning period for which one of a plurality of scanning lines is selected is divided into first and second half periods. A nonselection voltage for bringing a TFD into a nonconductive state for the first half period and a selection voltage for bringing the TFD into a conductive state for the second half period are supplied as a scanning signal to the scanning line. When an odd scanning line is selected, a right shift modulation method is applied to the pixels located on the relevant scanning line; when an even scanning line is selected, a left shift modulation method is applied to the pixels located on the relevant scanning line. Thus a data signal Xi is supplied to the relevant data line.
    Type: Grant
    Filed: July 10, 2001
    Date of Patent: November 23, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Satoshi Yatabe
  • Patent number: 6636071
    Abstract: A circuit for transmitting/receiving a logic signal through a capacitor is provided, which prevents signal delay and malfunction on the receiving circuit side. The power supply voltage of the buffer that transmits the logic signal in the transmitting circuit is enhanced to be larger than the power supply voltage of the buffer that inputs the logic signal in the receiving circuit. As a result, the amplitude of the logic signal at the input point is expanded from the clipping level according to the protection diodes, so that the signal delay, as well as the malfunction are prevented.
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: October 21, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Satoshi Yatabe
  • Patent number: 6636206
    Abstract: Electric power consumed in an operation of displaying a gray-scale image is reduced. One of a plurality of scanning lines is selected during one horizontal scanning period, and a selection voltage is applied to the scanning line during one of a first half period and a second half period that said horizontal scanning period has been divided into. When an intermediate gray level is displayed, the selection voltage is applied to a scanning line in an odd-numbered column during the second half period and the selection voltage is applied to a scanning line in an even-numbered column during the first half period.
    Type: Grant
    Filed: July 10, 2001
    Date of Patent: October 21, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Satoshi Yatabe
  • Patent number: 6633287
    Abstract: A power supply circuit is provided for supplying a scanning line selection voltage to an electro-optical device. The electro-optical device includes pixels disposed at intersections between a plurality of scanning lines and a plurality of data lines, a voltage generation circuit for generating a selection voltage having a positive polarity (or a negative polarity) with respect to the center voltage of voltages applied to the data lines, a capacitor for storing the selection voltage, and an inverter circuit for inverting the polarity of the voltage stored in the capacitor with respect to the median voltage, and outputting the resultant voltage as a selection voltage having a negative polarity (or a positive polarity if the selection voltage has a negative polarity).
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: October 14, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Satoshi Yatabe, Suguru Yamazaki, Katsunori Yamazaki
  • Patent number: 6556064
    Abstract: A voltage booster method and circuit reduce the number of capacitors required for a voltage boost. First, a first terminal of a first auxiliary capacitor is connected to a ground line and a second terminal of the first auxiliary capacitor is connected to the supply line of an input voltage. Second, a first terminal of a second auxiliary capacitor is connected to the ground line, the first terminal of the first auxiliary capacitor is switched to the supply line of the input voltage, and the second terminal of the first auxiliary capacitor is switched and connected to a second terminal of the second auxiliary capacitor. Third, the first terminal of the second auxiliary capacitor is switched to the second terminal of the first auxiliary capacitor, and the second terminal of the second auxiliary capacitor is switched and connected to the output line.
    Type: Grant
    Filed: March 8, 2000
    Date of Patent: April 29, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Satoshi Yatabe
  • Patent number: 6469570
    Abstract: A voltage supply circuit capable of starting up a system while maintaining symmetry of a high level selection signal VH and a low level selection signal VL, not requiring a multistage charge pump circuit, and capable of reducing the number of parts of the system, wherein generation circuits of VD and VH are comprised of chopper type booster type switching regulators, and switching timings of a VH generation circuit 12 and a VL generation circuit 13 are controlled so that a virtual reference voltage VS (VD/2) and a middle point potential between VH and VL become the same.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: October 22, 2002
    Assignees: Texas Instruments Japan Limited, Seiko Epson Corporation
    Inventors: Hiroyasu Inomata, Satoshi Yatabe
  • Publication number: 20020126114
    Abstract: Out of a display screen, only pixels at intersections of particular scanning lines and particular data lines are used as a display area. To save power, the particular scanning lines are selected one for each horizontal scanning period. For one of the two split halves of the one horizontal scanning period, the selected scanning line is supplied with a selection voltage, and the polarity of the selection voltage is inverted at least every two or more horizontal scanning periods. The scanning lines other than the particular scanning lines are supplied with a non-selection voltage, which is inverted at least every one vertical scanning period.
    Type: Application
    Filed: August 6, 2001
    Publication date: September 12, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Satoshi Yatabe
  • Publication number: 20020089634
    Abstract: A wiring substrate is formed of a plurality of metal wirings 14e formed on a substrate 7c. A guard wiring 29 fabricated of an electrically conductive oxide such as ITO is interposed between at least a pair of adjacent ones of a plurality of metal wirings 14e. When voltages V1, V2, V3, and V4 applied to the metal wirings 14e are related to be V1>V2 >V3 >V4, a guard wiring 29 is present between a metal wiring 14e functioning as an anode and a metal wiring 14e functioning as a cathode, and the anode metal wiring 14e is prevented from being corroded.
    Type: Application
    Filed: October 24, 2001
    Publication date: July 11, 2002
    Inventors: Yasuhito Aruga, Satoshi Yatabe, Kogo Endo, Norihito Harada
  • Publication number: 20020015030
    Abstract: This invention provides a system for driving a display device that uses only a longitudinally elongated region in a display screen as a display region, and limits the power consumption to a lower level.
    Type: Application
    Filed: July 18, 2001
    Publication date: February 7, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Satoshi Yatabe
  • Patent number: 6297622
    Abstract: A power supply circuit is provided which converts an input voltage into an output voltage and outputs the output voltage. The power supply circuit has resistive elements, switches, and capacitors. The resistive elements cause a fraction of the output voltage to develop. The switches are turned on or off in order to enable or disable flow of a current through the resistive elements. When the switches as well as a switch are turned on, the capacitors hold the voltage, which is the fraction of the output voltage developed due to the resistive elements. A control circuit controls the switch so that the voltage will be equal to a reference voltage. Even during a period during which the switches are off, the voltage nearly corresponds with the voltage developed during a period during which the switches are on.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: October 2, 2001
    Assignee: Seiko Epson Corporation
    Inventor: Satoshi Yatabe
  • Patent number: 6188395
    Abstract: A power source circuit which is suitable as a power source for use in driving a liquid crystal display, wherein on the basis of the power source electric potentials (VDD, VEE), the voltage is divided by voltage dividing resistors (R1 to R5), and passes through operational amplifiers (OP1 to OP4) that comprise voltage followers, so that output electric potentials (V1 to V5) are output. The power source electric potential (VDD) and the intermediate electric potential (Va) which is output from a voltage dividing circuit (S) are supplied to the operational amplifiers (OP1, OP2), and the intermediate electric potential (Va) and the power source electric potential (VEE) are supplied to the operational amplifiers (OP3, OP4).
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: February 13, 2001
    Assignee: Seiko Epson Corporation
    Inventor: Satoshi Yatabe
  • Patent number: 5442370
    Abstract: A matrix liquid crystal display device includes a first substrate with a plurality of common electrodes disposed thereon. A second substrate includes a plurality of second segment electrodes disposed thereon. A liquid crystal is sandwiched between the two substrates. A power circuit generates a plurality of voltage waveforms. A segment electrode driver receives at least a portion of the plurality of voltage waveforms to produce a voltage segment waveform in response thereto which are applied to the segment electrodes. A common electrode driver receives at least a portion of the plurality of waveforms and produces a common voltage waveform in response thereto.
    Type: Grant
    Filed: May 14, 1993
    Date of Patent: August 15, 1995
    Assignee: Seiko Epson Corporation
    Inventors: Katsunori Yamazaki, Satoshi Yatabe