Patents by Inventor Satosi Nakayama

Satosi Nakayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7504667
    Abstract: A technique of ensuring compatibility between the method of improving the light extraction efficiency by roughening the surface of a LED structure, and the method of avoiding the adverse effect of a low-cost electrode pad ((1) forming a current distribution layer by a transparent conductive film made of metal or metal oxide, and (2) forming a flip chip structure). A light emitting diode has at least an n-type semiconducting layer, an active layer composed of 30 or less quantum well layers, and a p-type semiconducting layer provided on a substrate, wherein the surface of the semiconductor lamination structure contains a flat portion and a plurality of bores.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: March 17, 2009
    Assignee: Hitachi Cable, Ltd.
    Inventors: Hajime Fujikura, Satosi Nakayama
  • Publication number: 20060273336
    Abstract: A technique of ensuring compatibility between the method of improving the light extraction efficiency by roughening the surface of a LED structure, and the method of avoiding the adverse effect of a low-cost electrode pad ((1) forming a current distribution layer by a transparent conductive film made of metal or metal oxide, and (2) forming a flip chip structure). A light emitting diode comprises at least an n-type semiconducting layer, an active layer composed of 30 or less quantum well layers, and a p-type semiconducting layer provided on a substrate, wherein the surface of the semiconductor lamination structure contains a flat portion and a plurality of bores.
    Type: Application
    Filed: September 29, 2005
    Publication date: December 7, 2006
    Inventors: Hajime Fujikura, Satosi Nakayama