Abstract: According to an embodiment, a semiconductor device includes a first circuit block, a first through-substrate via, and a back surface wiring. The first circuit block is provided on a surface side of a semiconductor substrate. The first through-substrate via is provided along a circumference of the first circuit block so as to separate the first circuit block from other circuit blocks. The first circuit block is provided so as to penetrate the surface of the semiconductor substrate. The first circuit block is isolated from the surroundings. The first circuit block has conductivity. The back surface wiring is provided on the back surface side of the semiconductor substrate. The back surface wiring is connected to the first through-substrate via. The back surface wiring connects the first through-substrate via to a power supply terminal or a shield potential terminal.

Abstract: A cell array has a plurality of memory cells arranged in a matrix. Each one terminal of a plurality of switching circuits is connected to a bit line. A leakage current compensating circuit has an output node connected in common to the other terminal of the switching circuit. The leakage current compensating circuit comprises a plurality of MOSFETs. Each MOSFET has the same conduction type as a MOSFET whose output node is directly connected to the bit line in the memory cell. Each MOSFET of the leakage current compensating circuit has a gate electrode connected to a first voltage node and a source electrode connected to a second voltage node, and thereby, being biased so that the MOSFET turns off.

Abstract: A cell array has a plurality of memory cells arranged in a matrix. Each one terminal of a plurality of switching circuits is connected to a bit line. A leakage current compensating circuit has an output node connected in common to the other terminal of the switching circuit. The leakage current compensating circuit comprises a plurality of MOSFETs. Each MOSFET has the same conduction type as a MOSFET whose output node is directly connected to the bit line in the memory cell. Each MOSFET of the leakage current compensating circuit has a gate electrode connected to a first voltage node and a source electrode connected to a second voltage node, and thereby, being biased so that the MOSFET turns off.

Abstract: Disclosed is a semiconductor device including a memory cell array, word lines, bit lines, and a signal difference determination circuit. In the memory cell array, memory cells each formed by connecting a MOS transistor and resistor in series are arranged in a matrix. The word lines are connected to the gates of the MOS transistors of the memory cells in the same row of the memory cell array. The bit lines are provided so as to correspond to the columns of the memory cell array. Each bit line is connected to one terminal of a corresponding one of the resistors of the memory cells in the same column. The signal difference determination circuit compares two output signals read to two bit lines from a pair of memory cells, thereby determining stored information in the pair of memory cells.

Abstract: Disclosed is a semiconductor device including a memory cell array, word lines, bit lines, and a signal difference determination circuit. In the memory cell array, memory cells each formed by connecting a MOS transistor and resistor in series are arranged in a matrix. The word lines are connected to the gates of the MOS transistors of the memory cells in the same row of the memory cell array. The bit lines are provided so as to correspond to the columns of the memory cell array. Each bit line is connected to one terminal of a corresponding one of the resistors of the memory cells in the same column. The signal difference determination circuit compares two output signals read to two bit lines from a pair of memory cells, thereby determining stored information in the pair of memory cells.

Abstract: The dimension measurement and management of a mask or a wafer are facilitated by using a dummy pattern having a configuration and arrangement capable of achieving a plurality of objects. In the entire region or a major region of an optional wiring layer on a semiconductor chip and in the space between the adjacent patterns in an actual pattern portion, dummy patterns for controlling the coverage and density of a pattern in the wiring layer are regularly arranged. All or some of the dummy patterns are dummy patterns for the dimension measurement including the main size (width and distance) required for the dimension management of the wiring layer.

Abstract: The dimension measurement and management of a mask or a wafer are facilitated by using a dummy pattern having a configuration and arrangement capable of achieving a plurality of objects. In the entire region or a major region of an optional wiring layer on a semiconductor chip and in the space between the adjacent patterns in an actual pattern portion, dummy patterns for controlling the coverage and density of a pattern in the wiring layer are regularly arranged. All or some of the dummy patterns are dummy patterns for the dimension measurement including the main size (width and distance) required for the dimension management of the wiring layer.