Abstract: A solid-state imaging device includes a sharing pixel block having k (where k is a natural number other than 1) pixel transistors corresponding to n (where n is a natural number other than 1) pixels and a row-selection circuit configured to select the pixel transistors every row in the sharing pixel block using logic of an address signal and a timing signal. In this solid-state imaging device, in a case of a 1/n row decimation operation in which a signal is read every n rows, the row-selection circuit simultaneously performs shutter operations for n rows corresponding to the k pixel transistors included in the sharing pixel block using an input of a simultaneous-shutter-operation signal.

Abstract: A solid-state imaging device includes: a pixel array unit wherein a unit pixel group with a portion of elements of a unit pixel being shared with a plurality of unit pixels is arrayed in a matrix form, the unit pixel having a detecting unit, a pixel signal generating unit, a transfer unit to transfer the charge, and an initializing unit to initialize the potential of the pixel signal generating unit; and a driving control unit; wherein the driving control unit controls blooming reduction potential which is the transfer control potential supplied to the transfer unit of the unit pixel to be thinned, so that the overflow charge at the detecting unit with the unit pixel to be thinned which has no shared relation with the unit pixel to be read transitions to a state readily transferable to the pixel signal generating unit side of the unit pixel to be thinned.

Abstract: A solid-state imaging device includes: a pixel array unit wherein a unit pixel group with a portion of elements of a unit pixel being shared with a plurality of unit pixels is arrayed in a matrix form, the unit pixel having a detecting unit, a pixel signal generating unit, a transfer unit to transfer the charge, and an initializing unit to initialize the potential of the pixel signal generating unit; and a driving control unit; wherein the driving control unit controls blooming reduction potential which is the transfer control potential supplied to the transfer unit of the unit pixel to be thinned, so that the overflow charge at the detecting unit with the unit pixel to be thinned which has no shared relation with the unit pixel to be read transitions to a state readily transferable to the pixel signal generating unit side of the unit pixel to be thinned.

Abstract: A solid-state imaging device includes a sharing pixel block having k (where k is a natural number other than 1) pixel transistors corresponding to n (where n is a natural number other than 1) pixels and a row-selection circuit configured to select the pixel transistors every row in the sharing pixel block using logic of an address signal and a timing signal. In this solid-state imaging device, in a case of a 1/n row decimation operation in which a signal is read every n rows, the row-selection circuit simultaneously performs shutter operations for n rows corresponding to the k pixel transistors included in the sharing pixel block using an input of a simultaneous-shutter-operation signal.