Abstract: A computing device 10 is disclosed herein. A base unit 12 is provided for housing a plurality of computing components and also may include an input/output device such as a keyboard. A display unit 20 can be pivotally coupled to the base unit 12 about a spine 26a. The display unit 20 may include a viewing surface 24. In addition, a flap 50 can be attached to at least one edge of the display 20 and extend outwardly from screen 24. Electronic components 46 may be housed within the flap 50. Alternatively, the electronic components 46 may be housed within the base unit 12 and electrically coupled back to the display units 20.

Abstract: A low profile and light weight keyboard for portable electronic devices, such as notebook computers. In specific embodiments, the present invention provides a low profile keyboard 218 where the keycap engaging members 202 extend unobstructed below the back plate or circuit board 204. The travel of the key below the back plate may be eliminated from the overall stowed keyboard thickness by popping up the keyboard or otherwise extending the keyboard to a deployed position having sufficient thickness to accommodate the travel of the engaging members 212 below the base 204.

Abstract: A low profile keyboard which can be deployed from a storage position and once deployed have the feel and travel of prior art keyboards using scissor type wobble control. An embodiment of the invention reduces the storage thickness in prior art designs by translating the flexible dome to a position under the keycap when in the stowed position and back to beneath the actuator mechanism when in the deployed position. Thus in the deployed position the space for the key travel and the dome does not contribute to the overall thickness of the keyboard.

Abstract: A deployable keyboard similar in size to those found in notebooks or subnotebooks of the prior art or a full size keyboard is provide for portable electronic devices, such as personal data assistants (PDAs) allowing greater flexibility and easier input for the user without compromising the PDAs small format. In other embodiments, laptops, notebooks, sub-notebooks and PDAs are provided with full function keyboards which approximate the size of a typical desktop computer keyboard when in use, but when in a non-use configuration they have significantly smaller dimensions. In one embodiment, a portable pen computer 100 is provided which includes a housing 102, and first and second keyboard sections 110, 112 having a plurality of alphanumeric and/or operational keys. Each of the keyboard sections are connected by a first hinge 108 for folding and attached to the housing with a second hinge 116 for permitting selective pivotal rotation for deployment from a storage position in the bottom portion of the housing.

Abstract: Preferred embodiments include silicon-on-insulator structures (30) and integrated circuits include a thin single crystal silicon layer (32) on a silicon dioxide layer (34) which is on a polysilicon layer (36) bonded to a surface-oxidized silicon substrate (42) by a glass layer (38). Also, single crystal silicon layers on oxide on polysilicon substrates and methods of fabrication are included in the preferred embodiments.

Abstract: A stacked CMOS structure is disclosed which uses buried N++ source and drain for the non-self-aligned bulk N-channel driver devices together with an oversized polygate on which a non-self aligned P-channel load device is made from a second layer of poly or recrystallized poly. The non-self aligned pair of stacked devices provides increased density of devices per unit area with a simple process at the cost of increased gate to source and gate to drain parasitic capacitances.

Abstract: A current source MOSFET is fabricated by forming a trench (36) in an n++ drain (source) region (32) and extending below the trench (36). A gate oxide layer (40) is disposed on the sidewalls of the trench (36) and a conductive region (38) formed in the bottom of the trench (36). A gate-to-source (gate-to-drain) contact (49) is then formed in the trench (36) and then a drain (source) contact (58) formed. The vertical gate structure defines a vertical channel region on all sides of the trench (36) to allow a wider devive to be fabricated in a smaller overall silicon area.

Abstract: The disclosure relates to a method for realizing a fully functional buried level of interconnect using only a single level of a silicide over N+ polycrystalline silicon, the latter serving as the gate material for both the N channel and P channel devices formed.

Abstract: The disclosure relates to a method for realizing a fully functional buried level of interconnect using only a single level of a silicide over N+ polycrystalline silicon, the latter serving as the gate material for both the N channel and P channel devices formed.

Abstract: A stacked CMOS structure is disclosed which uses buried N++ source and drain for the non-self-aligned bulk N-channel driver devices together with an oversized polygate on which a non-self aligned P-channel load device is made from a second layer of poly or recrystallized poly. The non-self aligned pair of stacked devices provides increased density of devices per unit area with a simple process at the cost of increased gate to source and gate to drain parasitic capicitances.