Abstract: An ultra-thin composite package for integrated circuits including a metal base with a cavity to support a die with a molded plastic cap cooperating with the base to encapsulate the die. A lead frame having a thinned inner portion or lead tip areas may also be used to further reduce the package thickness. Package thicknesses of about 20 mils (0.5 mm) or less can be readily achieved using this structure combination.

Abstract: An integrated circuit package assembly with a first die disposed over a first substrate having traces defined therein to provide electrical access to the first die. A heatsink is disposed over the substrate and the first die. A second die and a leadframe is disposed over the heatsink. The leadframe provides electrical access to the second die.

Abstract: A Thermal Ball Lead Integrated Package (Thermal BLIP) having improved thermal performance over prior art BLIPs is described. The BLIP combines ball and lead technologies to increase the interconnect density of the package but has relatively poor heat extraction capabilities. The Thermal BLIP is particularly well suited for high power and pin count integrated circuit devices. In an embodiment of the present invention, a heat sink is attached to the top surface of the die and extends through the package molding such that it is exposed to the ambient environment. Since the heat sink is integrated into the molding, the package size and footprint is not increased thereby limiting the cost increase of the package. This arrangement enables the use of high power devices in dense circuit board applications.

Abstract: A semiconductor component package assembly including an integral radio frequency and electromagnetic interference shield is disclosed herein. The assembly includes a support member which supports an IC chip and defines an array of conductive leads. An electrically conductive shield is positioned relative to the IC chip so as to form an integral RF/EMI barrier between the IC chip and the ambient surroundings of the overall assembly. In a preferred embodiment, the shield is formed from different layers of material and configured for electrical connection of at least one conductive layer to certain ones of the leads which may include one or more ground leads.

Abstract: An integrated circuit assembly includes a dielectric flex tape substrate defining a predetermined array of electrically conductive traces and an array of solder balls or solder columns electrically connected to the bottom surface of the flex tape substrate and the traces. An integrated circuit die having a series of input/output pads is supported on the substrate. In one embodiment, a plurality of electrically conductive leads are supported by the flex tape substrate in electrical isolation from and over the conductive traces. A first and second series of bonding wires electrically connect certain ones of the input/output terminals on the integrated circuit die to the electrically conductive leads and conductive traces, respectively. In other embodiments, one or more electrically isolated conductive layers are supported by the dielectric flex tape substrate over the traces and electrically conductive leads.

Abstract: An integrated circuit assembly includes an integrated circuit chip having a plurality of input/output terminals arranged at a surface thereof, and an electrically conductive layer connected to such surface of the integrated circuit chip. The layer is electrically conductive in thickness and electrically insulative in width and length. The assembly may further include a dielectric substrate connected to the layer such that the layer electrically connects respective terminals of the integrated circuit chip to respective electrically conductive traces of the dielectric substrate. An array of contacts may be electrically connected to the traces of the dielectric substrate.

Abstract: An integrated circuit assembly is disclosed herein. The assembly includes a dielectric substrate defining a predetermined array of electrically conductive traces and an array of solder balls electrically connected to the traces. An integrated circuit chip having a series of input/output pads is supported on the substrate. In one embodiment, a plurality of leadframe leads are supported by the substrate in electrical isolation from and over the conductive traces. First and second series of bonding wires electrically connect certain ones of the input/output pads on the IC chip to the leadframe leads and conductive traces. In other embodiments, one or more electrically isolated conductive layers are supported by the dielectric substrate over the traces and leadframe leads. The integrated circuit assembly, in accordance with any of these embodiments, provides a very high density electrical interconnection arrangement for the IC chip while retaining a small package footprint.

Abstract: A lead frame having layered conductive planes is disclosed for use in semiconductor devices. The lead frame includes a plurality of long leads each having a lead tip and a plurality of short leads. Electrically conductive layers are attached to the long leads around such that they don't cover the tips of the long leads and are radially inward of the short leads. The conductive layers are insulated from the long lead and each other by adhesive insulating layers. In a preferred embodiment, the top conductive layer has a smaller width than the bottom conducting layer and is positioned to expose an inner and outer ledge on the bottom conducting layer. The exposed outer ledge allows bonding to the shorter leads. The use of shorter leads decreases the amount of inductance in the leads. The conductive layers also may act as capacitors. In one embodiment of the present application the short leads may correspond to ground and/or power leads.

Abstract: An integrated circuit assembly is disclosed herein. The assembly includes a dielectric substrate defining a predetermined array of electrically conductive traces and an array of solder balls electrically connected to the traces. An integrated circuit chip having a series of input/output pads is supported on the substrate. In one embodiment, a plurality of leadframe leads are supported by the substrate in electrical isolation from and over the conductive traces. First and second series of bonding wires electrically connect certain ones of the input/output pads on the IC chip to the leadframe leads and conductive traces. In other embodiments, one or more electrically isolated conductive layers are supported by the dielectric substrate over the traces and leadframe leads. The integrated circuit assembly, in accordance with any of these embodiments, provides a very high density electrical interconnection arrangement for the IC chip while retaining a small package footprint.