Abstract: Aspects include a method for logic built-in self-testing (LBIST) for use in an integrated circuit with scan chains. The method includes programming a product control generator and a pattern generator with an LBIST pattern comprising at least a number of loops. The LBIST pattern is executed by generating scan-in test values for scan chains with the pattern generator and controlling at least one test parameter with the product control generator. Scan-out responses are collected from the scan chains in a signature register, and a start request is received from a chip tester. The LBIST is started in response to the start request. Test summary data is reported to the chip tester before the whole number of loops has been executed.

Abstract: Aspects include a system having logic built-in self-test (LBIST) circuitry for use in an integrated circuit with scan chains. The system includes a pattern generator configured for generating scan-in test values for said scan chains; a signature register configured for collecting scan-out responses from said scan chains after a clock sequence; an on-product control generator configured for controlling at least one test parameter; one or more microcode array or memory elements configured to receive inputs to initialize fields in the microcode array or memory elements; and a test controller. The test controller includes a reader component configured for reading test parameters from a field of the microcode array or the memory elements; and a programming component configured for configuring the on-product control generator and the pattern generator with a LBIST pattern according to the read test parameters.

Abstract: Aspects include a method for logic built-in self-testing (LBIST) for use in an integrated circuit with scan chains. The method includes programming a product control generator and a pattern generator with an LBIST pattern comprising at least a number of loops. The LBIST pattern is executed by generating scan-in test values for scan chains with the pattern generator and controlling at least one test parameter with the product control generator. Scan-out responses are collected from the scan chains in a signature register, and a start request is received from a chip tester. The LBIST is started in response to the start request. Test summary data is reported to the chip tester before the whole number of loops has been executed.

Abstract: A tool for determining unknown sources in a circuit design for exclusion from logic built-in self test (LBIST) verification for the circuit. Responsive to initializing each of one or more latches in one or more test channels of the circuit design being tested, the tool determines whether a latch of the one or more latches is corrupted by an unknown source. The tool gathers each of the one or more latches determined to be an unknown source after a capture clock phase. The tool performs a backward traverse of logic circuitry feeding each of the one or more latches determined to be an unknown source. The tool verifies that a fence on one or more unknown source nets associated with each of the one or more latches blocked the unknown source from contributing to a test signature.

Abstract: Aspects include a system having logic built-in self-test (LBIST) circuitry for use in an integrated circuit with scan chains. The system includes a pattern generator configured for generating scan-in test values for said scan chains; a signature register configured for collecting scan-out responses from said scan chains after a clock sequence; an on-product control generator configured for controlling at least one test parameter; one or more microcode array or memory elements configured to receive inputs to initialize fields in the microcode array or memory elements; and a test controller. The test controller includes a reader component configured for reading test parameters from a field of the microcode array or the memory elements; and a programming component configured for configuring the on-product control generator and the pattern generator with a LBIST pattern according to the read test parameters.

Abstract: Aspects include a system having logic built-in self-test (LBIST) circuitry for use in an integrated circuit with scan chains. The system includes a pattern generator configured for generating scan-in test values for said scan chains; a signature register configured for collecting scan-out responses from said scan chains after a clock sequence; an on-product control generator configured for controlling at least one test parameter; one or more microcode array or memory elements configured to receive inputs to initialize fields in the microcode array or memory elements; and a test controller. The test controller includes a reader component configured for reading test parameters from a field of the microcode array or the memory elements; and a programming component configured for configuring the on-product control generator and the pattern generator with a LBIST pattern according to the read test parameters.

Abstract: A tool for determining unknown sources in a circuit design for exclusion from logic built-in self test (LBIST) verification for the circuit. Responsive to initializing each of one or more latches in one or more test channels of the circuit design being tested, the tool determines whether a latch of the one or more latches is corrupted by an unknown source. The tool gathers each of the one or more latches determined to be an unknown source after a capture clock phase. The tool performs a backward traverse of logic circuitry feeding each of the one or more latches determined to be an unknown source. The tool verifies that a fence on one or more unknown source nets associated with each of the one or more latches blocked the unknown source from contributing to a test signature.

Abstract: Aspects include a method for logic built-in self-testing (LBIST) for use in an integrated circuit with scan chains. The method includes programming a product control generator and a pattern generator with an LBIST pattern comprising at least a number of loops. The LBIST pattern is executed by generating scan-in test values for scan chains with the pattern generator and controlling at least one test parameter with the product control generator. Scan-out responses are collected from the scan chains in a signature register, and a start request is received from a chip tester. The LBIST is started in response to the start request. Test summary data is reported to the chip tester before the whole number of loops has been executed.

Abstract: Aspects include a system having logic built-in self-test (LBIST) circuitry for use in an integrated circuit with scan chains. The system includes a pattern generator configured for generating scan-in test values for said scan chains; a signature register configured for collecting scan-out responses from said scan chains after a clock sequence; an on-product control generator configured for controlling at least one test parameter; one or more microcode array or memory elements configured to receive inputs to initialize fields in the microcode array or memory elements; and a test controller. The test controller includes a reader component configured for reading test parameters from a field of the microcode array or the memory elements; and a programming component configured for configuring the on-product control generator and the pattern generator with a LBIST pattern according to the read test parameters.

Abstract: Aspects include a method for logic built-in self-testing (LBIST) for use in an integrated circuit with scan chains. The method includes programming a product control generator and a pattern generator with an LBIST pattern comprising at least a number of loops. The LBIST pattern is executed by generating scan-in test values for scan chains with the pattern generator and controlling at least one test parameter with the product control generator. Scan-out responses are collected from the scan chains in a signature register, and a start request is received from a chip tester. The LBIST is started in response to the start request. Test summary data is reported to the chip tester before the whole number of loops has been executed.

Abstract: A tool for determining unknown sources in a circuit design for exclusion from logic built-in self test (LBIST) verification for the circuit. The tool initializes, by one or more computer processors, one or more nets contained in an initial nets list, wherein the initial nets list is a representation of a circuit design being tested. The tool removes, by one or more computer processors, the one or more nets initialized in response to initialization of each of one or more latches in one or more test channels of the circuit design being tested. The tool determines, by one or more computer processors, whether a latch of the one or more latches is corrupted by an unknown source.

Abstract: A tool for determining unknown sources in a circuit design for exclusion from logic built-in self test (LBIST) verification for the circuit. The tool initializes, by one or more computer processors, one or more nets contained in an initial nets list, wherein the initial nets list is a representation of a circuit design being tested. The tool removes, by one or more computer processors, the one or more nets initialized in response to initialization of each of one or more latches in one or more test channels of the circuit design being tested. The tool determines, by one or more computer processors, whether a latch of the one or more latches is corrupted by an unknown source.

Abstract: A tool for determining unknown sources in a circuit design for exclusion from logic built-in self test (LBIST) verification for the circuit. The tool determines, by one or more computer processors, an initial nets list, wherein the initial nets list is a representation of a circuit design being tested. The tool initializes, by one or more computer processors, one or more nets contained in the initial nets list. The tool removes, by one or more computer processors, the one or more nets initialized in response to initialization of each of one or more latches in one or more test channels of the circuit design being tested. The tool determines, by one or more computer processors, whether a latch of the one or more latches is corrupted by an unknown source.