Abstract: A network of sensors is associated with a power distribution network. Sensors are positioned at each connecting line in the vicinity of each node of the power distribution network. The sensors regularly report the following measured data to the central processing unit: a geographical position of each sensor, direction of the energy flow relative to the nearest node; and value of RMS current synchronously measured over the entire network and averaged over chosen averaging period. The central processing unit includes an arrangement for receiving the measured data and using this data for constructing and updating a graph and a state of the power distribution network.

Abstract: Provided is a portable transport apparatus having an enclosure for containing an item to be transported, a RFID reader connected to a near field antenna disposed within the enclosure for a first RFID reading of an area inside the enclosure and to a far field antenna disposed on the enclosure for a second RFID reading of an area outside the enclosure, and a wireless communication module, and a method of use of the portable transport apparatus.

Abstract: A network of sensors is associated with a power distribution network. Sensors are positioned at each connecting line in the vicinity of each node of the power distribution network. The sensors regularly report the following measured data to the central processing unit: a geographical position of each sensor, direction of the energy flow relative to the nearest node; and value of RMS current synchronously measured over the entire network and averaged over chosen averaging period. The central processing unit includes an arrangement for receiving the measured data and using this data for constructing and updating a graph and a state of the power distribution network.

Abstract: A system, method, and a computer readable for protecting content of a memory page are disclosed. The method includes determining a start of a semi-synchronous memory copy operation. A range of addresses is determined where the semi-synchronous memory copy operation is being performed. An issued instruction that removes a page table entry is detected. The method further includes determining whether the issued instruction is destined to remove a page table entry associated with at least one address in the range of addresses. In response to the issued instruction being destined to remove the page table entry, the execution of the issued instruction is stalled until the semi-synchronous memory copy operation is completed.

Abstract: A system, method, and a computer readable for inserting data into a cache memory based on information in a semi-synchronous memory copy instruction are disclosed. The method comprises determining a start of a semi-synchronous memory copy operation. The semi-synchronous memory copy operation is checked for a given value in at least one cache injection bit. In response to the given value in the cache injection bit, a predefined number of lines of destination data is copied into at least one level of cache memory.

Abstract: A method, processing node, and computer readable medium for propagating data using mirrored lock caches are disclosed. The method includes coupling a first mirrored lock cache associated with a first processing node to a bus that is communicatively coupled to at least a second mirrored lock cache associated with a second processing node in a multi-processing system. The method further includes receiving, by the first mirrored lock cache, data from a processing node. The data is then mirrored automatically so that the same data is available locally at the second mirrored lock cache for use by the second processing node.

Abstract: A system, method, and computer program product for semi-synchronously copying data from a first portion of memory to a second portion of memory are disclosed. The method comprises receiving, in a processor, a call for a semi-synchronous memory copy operation. The semi-synchronous memory copy operation preserves temporal persistence of validity for a virtual source address corresponding to a source location in a memory and a virtual target address corresponding to a target location in the memory by setting a flag bit. The call includes at least the virtual source address, the virtual target address, and an indicator identifying a number of bytes to be copied. The memory copy operation is placed in a queue for execution by a memory controller. The queue is coupled to the memory controller. At least one subsequent instruction is continued to be executed as the subsequent instruction becomes available from an instruction pipeline.

Abstract: A method, system and computer-usable medium are presented for pausing a software thread in a process. An instruction from a first software thread in the process is sent to an Instruction Sequencing Unit (ISU) in a processing unit. The instruction from the first software thread is then sent to a first instruction holding latch from a plurality of instruction holding latches in the ISU. The first instruction holding latch, which contains the instruction from the first software thread, is then selectively frozen, such that the instruction from the first software thread is unable to pass to an execution unit in a processor core while the first instruction holding latch is frozen. This causes the entire first software thread to likewise be frozen, while allowing other software threads in the process to continue executing.

Abstract: A method for improving the reliability of host data stored on Fibre Channel attached storage subsystems by performing end-to-end data integrity checks. When a read or write operation is initiated, an initial checksum for data in the read/write operation is generated and associated with the data, wherein the association exists through a plurality of layers of software and attached storage subsystems. The initial checksum is passed with the data in the read/write path. When a layer of software in the read/write path receives the initial checksum and data, the layer performs an integrity check of the data, which includes generating another checksum and comparing it to the initial checksum. If the checksums do not match, the read/write operation fails and the error is logged. If the checksums match, the integrity check is repeated through each layer in the read/write path to enable detecting data corruption at the point of source.

Abstract: An Ethernet adapter is disclosed. The Ethernet adapter comprises a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor. The plurality of layers include a demultiplexing mechanism to allow for partitioning of the processor. A Host Ethernet Adapter (HEA) is an integrated Ethernet adapter providing a new approach to Ethernet and TCP acceleration. A set of TCP/IP acceleration features have been introduced in a toolkit approach: Servers TCP/IP stacks use these accelerators when and as required. The interface between the server and the network interface controller has been streamlined by bypassing the PCI bus. The HEA supports network virtualization. The HEA can be shared by multiple OSs providing the essential isolation and protection without affecting its performance.

Abstract: A multiprocessor data processing system (MDPS) with a weakly-ordered architecture providing processing logic for substantially eliminating issuing sync instructions after every store instruction of a well-behaved application. Instructions of a well-behaved application are translated and executed by a weakly-ordered processor. The processing logic includes a lock address tracking utility (LATU), which provides an algorithm and a table of lock addresses, within which each lock address is stored when the lock is acquired by the weakly-ordered processor. When a store instruction is encountered in the instruction stream, the LATU compares the target address of the store instruction against the table of lock addresses. If the target address matches one of the lock addresses, indicating that the store instruction is the corresponding unlock instruction (or lock release instruction), a sync instruction is issued ahead of the store operation.

Abstract: Methods, systems, and computer program products are provided for migrating an operating system from a source computer to a destination computer. Some embodiments include identifying a destination adapter of the destination computer that is coupled for data communications to a SAN that is also coupled for data communications to a source adapter of the source computer, logging off a virtual port name of the source adapter from the login manager, deregistering the virtual port name from the source adapter, registering the virtual port name with the destination adapter, and logging on the destination adapter to the login manager with the virtual port name. Typical embodiments also include transferring the operating system from the source computer to the destination computer.

Abstract: A method for sharing resources in one or more data processing systems is disclosed. The method comprises a data processing system defining a plurality of logical partitions with respect to one or more processing units of one or more data processing systems, wherein a selected logical partition among the plurality of logical partitions includes a physical input/output adapter and each of the plurality of logical partitions includes a virtual input/output adapter. The data processing system then assigns each of one or more of the virtual input/output adapters a respective virtual network address and VLAN tag and shares resources by communicating data between a logical partition that is not the selected logical partition and an external network node via the virtual input/output adapter of the selected partition and the physical input/output adapter of the selected logical partition using packets containing VLAN tags and said virtual network address.

Abstract: A method, system and computer program product for transitioning network traffic between logical partitions in one or more data processing systems are disclosed. The method includes defining a plurality of logical partitions with respect to one or more processing units of one or more data processing systems and dynamically reallocating resources from a second partition to a first partition among the plurality of logical partitions. Packets awaiting processing are transferred from the second partition to the first partition and processed on the first partition.

Abstract: The present invention relates to means, a method and a computer program product of administrating in a computer system a global data element shared by a multitude of exploiters within said computer system for reducing contention among said exploiters. It is suggested to execute a first step by a first exploiter of accumulating one or a multitude of modifications performed by said first exploiter with respect to the current contents of said global data element into a first local data element not shared by other exploiters. In a second step executed by the first exploiter a size of the accumulated modifications in the first local data element with respect to the current contents of the global data element is determined. Moreover it is determined, if said size exceeds a specified quantum. If said size exceeds the specified quantum, the global data element is updated with the accumulated modifications as new contents.