Patents by Inventor Satya Someswara Kaushik YANAMANDRA

Satya Someswara Kaushik YANAMANDRA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Short detection circuit
    Patent number: 11531070
    Abstract: Aspects of the present disclosure provide for a circuit. In at least some examples, the circuit includes an output node at which a voltage for transmission via a differential conductor is present. The circuit further includes a first pull-up network coupled between a voltage supply node and the output node and configured to include a first amount of resistance. The circuit further includes a second pull-up network coupled between a voltage supply node and the output node and configured to include a second amount of resistance. The circuit further includes a comparator having a first input terminal coupled to the output node, a second input terminal configured to receive a reference voltage, and an output terminal configured to output a comparison result.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: December 20, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Satya Someswara Kaushik Yanamandra, Soumya Chandramouli, Michael Shin-Chyr Lu
  • SHORT DETECTION CIRCUIT
    Publication number: 20210223330
    Abstract: Aspects of the present disclosure provide for a circuit. In at least some examples, the circuit includes an output node at which a voltage for transmission via a differential conductor is present. The circuit further includes a first pull-up network coupled between a voltage supply node and the output node and configured to include a first amount of resistance. The circuit further includes a second pull-up network coupled between a voltage supply node and the output node and configured to include a second amount of resistance. The circuit further includes a comparator having a first input terminal coupled to the output node, a second input terminal configured to receive a reference voltage, and an output terminal configured to output a comparison result.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 22, 2021
    Inventors: Satya Someswara Kaushik YANAMANDRA, Soumya CHANDRAMOULI, Michael Shin-Chyr LU