Patents by Inventor SATYAJIT SARANGI

SATYAJIT SARANGI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10796397
    Abstract: A mechanism is described for facilitating dynamic runtime transformation of graphics processing commands for improved graphics performance on computing devices. A method of embodiments, as described herein, includes detecting a command stream associated with an application, where the command stream includes dispatches. The method may further include evaluating processing parameters relating to each of the dispatches, where evaluating further includes associating a first plan with one or more of the dispatches to transform the command stream into a transformed command stream. The method may further include associating, based on the first plan, a second plan to the one or more of the dispatches, where the second plan represents the transformed command stream. The method may further include executing the second plan, where execution of the second plan includes processing the transformed command stream in lieu of the command stream.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: October 6, 2020
    Assignee: INTEL CORPORATION
    Inventors: James A. Valerio, Abhishek Venkatesh, Satyajit Sarangi, Michael Apodaca, Thomas F. Raoux, Hashem Hashemi, Rama S. B. Harihara
  • Patent number: 10318292
    Abstract: Systems and methods may process a single atomic operation. An instruction set may be generated to replace a plurality of atomic operations with a single atomic operation. The instruction set may include an accumulation instruction to compute a prefix sum for a plurality of initial values associated with a plurality of processing lanes to generate a plurality of accumulated values. The instruction set may also include a broadcast instruction to return a pre-existing value to be added with each of the plurality of accumulated values to generate a plurality of intermediate accumulated values. In one example, a graphics processor may execute the instruction set to process the single atomic operation.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Satyajit Sarangi, Thomas F. Raoux, Guei-Yuan Lueh, Subramaniam Maiyuran
  • Patent number: 9632979
    Abstract: An apparatus and method are described for performing a prefix sum. For example, one embodiment of an apparatus comprises: a graphics processor unit comprising one or more execution units to execute single instruction multiple data (SIMD) instructions, the GPU to be provided with a plurality of data elements as input for a prefix sum operation; a first register of the GPU to store the plurality of data elements in specified data element positions; and the one or more execution units to perform a series of single instruction multiple data (SIMD) operations using the plurality of data elements, the SIMD operations performed using regioning techniques to generate the prefix sum, the SIMD operations including a first plurality of simultaneous addition operations to add specified data elements to generate intermediate results and further including a second plurality of simultaneous addition operations to add the intermediate results to other intermediate results to generate the prefix sum.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Satyajit Sarangi, Thomas F. Raoux
  • Publication number: 20160364828
    Abstract: A mechanism is described for facilitating dynamic runtime transformation of graphics processing commands for improved graphics performance on computing devices. A method of embodiments, as described herein, includes detecting a command stream associated with an application, where the command stream includes dispatches. The method may further include evaluating processing parameters relating to each of the dispatches, where evaluating further includes associating a first plan with one or more of the dispatches to transform the command stream into a transformed command stream. The method may further include associating, based on the first plan, a second plan to the one or more of the dispatches, where the second plan represents the transformed command stream. The method may further include executing the second plan, where execution of the second plan includes processing the transformed command stream in lieu of the command stream.
    Type: Application
    Filed: June 12, 2015
    Publication date: December 15, 2016
    Applicant: INTEL CORPORATION
    Inventors: James A. Valerio, Abhishek Venkatesh, Satyajit Sarangi, Michael Apodaca, Thomas F. Raoux, Hashem Hashemi, Rama S.B. Harihara
  • Publication number: 20160350262
    Abstract: An apparatus and method are described for performing a prefix sum. For example, one embodiment of an apparatus comprises: a graphics processor unit comprising one or more execution units to execute single instruction multiple data (SIMD) instructions, the GPU to be provided with a plurality of data elements as input for a prefix sum operation; a first register of the GPU to store the plurality of data elements in specified data element positions; and the one or more execution units to perform a series of single instruction multiple data (SIMD) operations using the plurality of data elements, the SIMD operations performed using regioning techniques to generate the prefix sum, the SIMD operations including a first plurality of simultaneous addition operations to add specified data elements to generate intermediate results and further including a second plurality of simultaneous addition operations to add the intermediate results to other intermediate results to generate the prefix sum.
    Type: Application
    Filed: June 1, 2015
    Publication date: December 1, 2016
    Inventors: SATYAJIT SARANGI, THOMAS F. RAOUX
  • Publication number: 20160139934
    Abstract: Systems and methods may process a single atomic operation. An instruction set may be generated to replace a plurality of atomic operations with a single atomic operation. The instruction set may include an accumulation instruction to compute a prefix sum for a plurality of initial values associated with a plurality of processing lanes to generate a plurality of accumulated values. The instruction set may also include a broadcast instruction to return a pre-existing value to be added with each of the plurality of accumulated values to generate a plurality of intermediate accumulated values. In one example, a graphics processor may execute the instruction set to process the single atomic operation.
    Type: Application
    Filed: November 17, 2014
    Publication date: May 19, 2016
    Applicant: Intel Corporation
    Inventors: SATYAJIT SARANGI, THOMAS F. RAOUX, GUEI-YUAN LUEH, SUBRAMANIAM MAIYURAN