Patents by Inventor Satyaki Koneru
Satyaki Koneru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190171497Abstract: Methods, systems and apparatuses for graph processing are disclosed. One graph streaming processor includes a thread manager, wherein the thread manager is operative to dispatch operation of the plurality of threads of a plurality of thread processors before dependencies of the dependent threads have been resolved, maintain a scorecard of operation of the plurality of threads of the plurality of thread processors, and provide an indication to at least one of the plurality of thread processors when a dependency between the at least one of the plurality of threads that a request has or has not been satisfied. Further, a producer thread provides a response to the dependency when the dependency has been satisfied, and each of the plurality of thread processors is operative to provide processing updates to the thread manager, and provide queries to the thread manager upon reaching a dependency.Type: ApplicationFiled: February 8, 2019Publication date: June 6, 2019Applicant: ThinCl, Inc.Inventors: Lokesh Agarwal, Sarvendra Govindammagari, Venkata Ganapathi Puppala, Satyaki Koneru
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Patent number: 10311542Abstract: The claimed invention discloses system comprising a plurality of logical nodes comprised in a single or plurality of stages, with defined properties and resources associated with each node, for reducing compute resources, said system further comprising: at least a recirculating ring buffer holding only any one of a control information, input, and, or out data necessary to stream a temporary data between node and, or nodes in an execution graph, thereby reducing size of said recirculating ring buffer; said recirculating ring buffer being sufficiently reduced in size to reside in an on-chip cache, such that any one of the control information, input, and, or out data between node and, or nodes need not be stored in memory; wherein the control information further comprises a command related to invalidating any one of the input and, or out data held in a recirculating ring data buffer, clearing the buffer of tasked data; and wherein a producer is stalled from writing any more control information into a recirculatiType: GrantFiled: March 6, 2017Date of Patent: June 4, 2019Assignee: THINCI, Inc.Inventors: Val G. Cook, Satyaki Koneru, Ke Yin, Dinakar C. Munagala
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Publication number: 20180253890Abstract: The claimed invention discloses system comprising a plurality of logical nodes comprised in a single or plurality of stages, with defined properties and resources associated with each node, for reducing compute resources, said system further comprising: at least a recirculating ring buffer holding only any one of a control information, input, and, or out data necessary to stream a temporary data between node and, or nodes in an execution graph, thereby reducing size of said recirculating ring buffer; said recirculating ring buffer being sufficiently reduced in size to reside in an on-chip cache, such that any one of the control information, input, and, or out data between node and, or nodes need not be stored in memory; wherein the control information further comprises a command related to invalidating any one of the input and, or out data held in a recirculating ring data buffer, clearing the buffer of tasked data; and wherein a producer is stalled from writing any more control information into a recirculatiType: ApplicationFiled: March 6, 2017Publication date: September 6, 2018Inventors: Val G. Cook, Satyaki Koneru, Ke Yin, Dinakar C. Munagala
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Publication number: 20170365237Abstract: Methods, systems and apparatuses for processing a plurality of threads of a single-instruction multiple data (SIMD) group are disclosed. One method includes initializing a current instruction pointer of the SIMD group, initializing a thread instruction pointer for each of the plurality of threads of the SIMD group including setting a flag for each of the plurality of threads, determining whether a current instruction of the processing includes a conditional branch, resetting a flag of each thread of the plurality of threads that fails a condition of the conditional branch, and setting the thread instruction pointer for each of the plurality of threads that fails the condition of the conditional branch to a jump instruction pointer, and incrementing the current instruction pointer and each thread instruction pointer of the threads that do not fail, if at least one of the threads do not fail the condition.Type: ApplicationFiled: August 17, 2017Publication date: December 21, 2017Applicant: ThinCl, Inc.Inventors: Satyaki Koneru, Ke Yin
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Publication number: 20170193630Abstract: Methods, systems and apparatuses for selecting graphics data of a server system for transmission are disclosed. One method includes reading data from memory of the server system, checking if the data is being read for the first time, checking if the data was written by a processor of the server system during processing, comprising checking if the data is available on a client system or present in a transmit buffer, placing the data in the transmit buffer if the data is being read for the first time and was not written by the processor during the processing as determined by the checking if the data was written by the processor of the server system during processing, wherein if the data is being read for the first time and was written by the processor of the server system during processing the data is not placed in the transmit buffer.Type: ApplicationFiled: March 22, 2017Publication date: July 6, 2017Applicant: ThinCl, Inc.Inventors: Satyaki Koneru, Ke Yin, Dinakar C. Munagala
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Patent number: 9640150Abstract: Methods, systems and apparatuses for selecting graphics data of a server system for transmission are disclosed. One method includes reading data from memory of the server system, checking if the data is being read for the first time, checking if the data was written by a processor of the server system during processing, comprising checking if the data is available on a client system or present in a transmit buffer, placing the data in the transmit buffer if the data is being read for the first time and was not written by the processor during the processing as determined by the checking if the data was written by the processor of the server system during processing, wherein if the data is being read for the first time and was written by the processor of the server system during processing the data is not placed in the transmit buffer.Type: GrantFiled: May 19, 2016Date of Patent: May 2, 2017Assignee: ThinCI, Inc.Inventors: Satyaki Koneru, Ke Yin, Dinakar C. Munagala
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Patent number: 9589388Abstract: Embodiments disclosed include a mechanism in a system and method for significantly reducing power consumption by reducing computation and bandwidth. This mechanism is particularly applicable for modern 3D synthetic images which contain high pixel overdraw and dynamically generated intermediates images. Only blocks of computation which contribute to the final image are performed. This is accomplished by rendering in reverse order and by performing multiple visibility sort in a streaming fashion through the pipeline. Rendering of dynamically generated intermediate images is performed sparsely by projecting texture coordinates from a current image back into one or more dependent images in a recursive manner. The newly computed pixel values are then filtered and control is returned to the sampling shader of the current image. When only visible pixels are projected optimal computation is performed. Several implementations are presented with increasing efficiency.Type: GrantFiled: July 9, 2014Date of Patent: March 7, 2017Assignee: ThinCI, Inc.Inventors: Val G. Cook, Satyaki Koneru, Ke Yin, Dinakar C. Munagala
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Publication number: 20160267889Abstract: Methods, systems and apparatuses for selecting graphics data of a server system for transmission are disclosed. One method includes reading data from memory of the server system, checking if the data is being read for the first time, checking if the data was written by a processor of the server system during processing, comprising checking if the data is available on a client system or present in a transmit buffer, placing the data in the transmit buffer if the data is being read for the first time and was not written by the processor during the processing as determined by the checking if the data was written by the processor of the server system during processing, wherein if the data is being read for the first time and was written by the processor of the server system during processing the data is not placed in the transmit buffer.Type: ApplicationFiled: May 19, 2016Publication date: September 15, 2016Applicant: ThinCl, Inc.Inventors: Satyaki Koneru, Ke Yin, Dinakar C. Munagala
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Patent number: 9373152Abstract: Methods, systems and apparatuses for selecting graphics data of a server system for transmission are disclosed. One method includes a plurality of graphic render passes, wherein one or more of the graphics render passes includes reading data from graphics memory of the server system. The data read from the graphics memory is placed in a transmit buffer if the data is being read for the first time, and was not written by a processor of the server system. One system includes a server system including graphics memory, a frame buffer and a processor. The server system is operable to read data from the graphics memory. The server system is operable to place the data in a transmit buffer if the data is being read for the first time, and was not written by the processor during rendering.Type: GrantFiled: May 25, 2014Date of Patent: June 21, 2016Assignee: ThinCI, Inc.Inventors: Satyaki Koneru, Ke Yin, Dinakar C. Munagala
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Publication number: 20140253563Abstract: Methods, systems and apparatuses for selecting graphics data of a server system for transmission are disclosed. One method includes a plurality of graphic render passes, wherein one or more of the graphics render passes includes reading data from graphics memory of the server system. The data read from the graphics memory is placed in a transmit buffer if the data is being read for the first time, and was not written by a processor of the server system. One system includes a server system including graphics memory, a frame buffer and a processor. The server system is operable to read data from the graphics memory. The server system is operable to place the data in a transmit buffer if the data is being read for the first time, and was not written by the processor during rendering.Type: ApplicationFiled: May 25, 2014Publication date: September 11, 2014Applicant: THINCL, INC.Inventors: Satyaki Koneru, Ke Yin, Dinakar C. Munagala
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Patent number: 8804757Abstract: In some embodiments, a motion estimation method and engine are provided. A motion estimation engine may, for example, compare source blocks from a source frame against reference blocks in a reference frame to find a suitable match for the source block. According to some embodiments, groups of reference blocks are compared at the same time against the source block, with search units within each group being selected for comparison simultaneously using both a fixed path navigation and an adaptive path navigation.Type: GrantFiled: December 26, 2007Date of Patent: August 12, 2014Assignee: Intel CorporationInventors: Ning Lu, Hong Jiang, Satyaki Koneru
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Patent number: 8754900Abstract: Methods, systems and apparatuses for selecting graphics data of a server system for transmission are disclosed. One method includes reading data from graphics memory of the server system. The data read from the graphics memory is placed in a transmit buffer if the data is being read for the first time, and was not written by a processor of the server system. One system includes a server system including graphics memory, a frame buffer and a processor. The server system is operable to read data from the graphics memory. The server system is operable to place the data in a transmit buffer if the data is being read for the first time, and was not written by the processor during rendering.Type: GrantFiled: June 16, 2011Date of Patent: June 17, 2014Inventors: Satyaki Koneru, Ke Yin, Dinakar Munagala
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Publication number: 20110310105Abstract: Methods, systems and apparatuses for selecting graphics data of a server system for transmission are disclosed. One method includes reading data from graphics memory of the server system. The data read from the graphics memory is placed in a transmit buffer if the data is being read for the first time, and was not written by a processor of the server system. One system includes a server system including graphics memory, a frame buffer and a processor. The server system is operable to read data from the graphics memory. The server system is operable to place the data in a transmit buffer if the data is being read for the first time, and was not written by the processor during rendering.Type: ApplicationFiled: June 16, 2011Publication date: December 22, 2011Applicant: THINCI INC.Inventors: Satyaki Koneru, Ke Yin, Dinakar Munagala
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Publication number: 20090168881Abstract: In some embodiments, a motion estimation method and engine are provided.Type: ApplicationFiled: December 26, 2007Publication date: July 2, 2009Inventors: Ning Lu, Hong Jiang, Satyaki Koneru
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Publication number: 20050225557Abstract: A texture data reading apparatus includes a cache memory including a plurality of read ports and a plurality of regions to store pixel texture data. An address comparator includes a plurality of input ports to receive incoming pixels, wherein the address comparator compares the memory addresses associated with the incoming pixels to determine which regions of cache memory are accessed. A cache lookup device accesses new texture data from the cache memory for the incoming pixels in the same clock cycle in response to the number of memory regions accessed being less than or equal to the number of cache memory read ports.Type: ApplicationFiled: June 7, 2005Publication date: October 13, 2005Inventors: Satyaki Koneru, Steven Spangler, Val Cook
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Patent number: 6924812Abstract: A texture data reading apparatus includes a cache memory including a plurality of read ports and a plurality of regions to store pixel texture data. An address comparator includes a plurality of input ports to receive incoming pixels, wherein the address comparator compares the memory addresses associated with the incoming pixels to determine which regions of cache memory are accessed. A cache lookup device accesses new texture data from the cache memory for the incoming pixels in the same clock cycle in response to the number of memory regions accessed being less than or equal to the number of cache memory read ports.Type: GrantFiled: December 24, 2002Date of Patent: August 2, 2005Assignee: Intel CorporationInventors: Satyaki Koneru, Steven J. Spangler, Val G. Cook
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Publication number: 20040119719Abstract: A texture data reading apparatus includes a cache memory including a plurality of read ports and a plurality of regions to store pixel texture data. An address comparator includes a plurality of input ports to receive incoming pixels, wherein the address comparator compares the memory addresses associated with the incoming pixels to determine which regions of cache memory are accessed. A cache lookup device accesses new texture data from the cache memory for the incoming pixels in the same clock cycle in response to the number of memory regions accessed being less than or equal to the number of cache memory read ports.Type: ApplicationFiled: December 24, 2002Publication date: June 24, 2004Inventors: Satyaki Koneru, Steven J. Spangler, Val G. Cook
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Patent number: 6693637Abstract: Embodiments of the present invention provide a method and apparatus for determining the zones that a polygon overlaps to minimize the bins that are updated during binning and reduce the number of polygons to be set up in the render phase. The polygons supported include, but are not limited to, points, lines, triangles and rectangles. Each zone has associated with it a batch buffer to which data is written back for the polygons that overlap that zone. This data includes the setting up of state and the indices for those polygons. Since the zones that a polygon overlaps is precisely determined, the data written back is minimized and the polygons to be set up during the render phase is optimally reduced.Type: GrantFiled: December 31, 2001Date of Patent: February 17, 2004Assignee: Intel CorporationInventors: Satyaki Koneru, Sajjad A. Zaidi
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Publication number: 20030122819Abstract: Embodiments of the present invention provide a method and apparatus for determining the zones that a polygon overlaps to minimize the bins that are updated during binning and reduce the number of polygons to be set up in the render phase. The polygons supported include, but are not limited to, points, lines, triangles and rectangles. Each zone has associated with it a batch buffer to which data is written back for the polygons that overlap that zone. This data includes the setting up of state and the indices for those polygons. Since the zones that a polygon overlaps is precisely determined, the data written back is minimized and the polygons to be set up during the render phase is optimally reduced.Type: ApplicationFiled: December 31, 2001Publication date: July 3, 2003Inventors: Satyaki Koneru, Sajjad A. Zaidi
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Publication number: 20030122850Abstract: Embodiments of the present invention provide a method and apparatus for determining the zones that a polygon overlaps to minimize the bins that are updated during binning and reduce the number of polygons to be set up in the render phase. The polygons supported include, but are not limited to, points, lines, triangles and rectangles. Each zone has associated with it a batch buffer to which data is written back for the polygons that overlap that zone. This data includes the setting up of state and the indices for those polygons. Since the zones that a polygon overlaps is precisely determined, the data written back is minimized and the polygons to be set up during the render phase is optimally reduced.Type: ApplicationFiled: December 28, 2001Publication date: July 3, 2003Inventors: Satyaki Koneru, Sajjad A. Zaidi