Abstract: The present disclosure provides a motor drive integrated on-board charger to reduce the quantity of components in an electric system of an electric vehicle. Reduction of components is achieved by utilizing the motor and the motor driving inverter as a part of the on-board charger in the charging mode. By controlling relays, electrical connections of the system may be reconfigured according to its mode of operation. In one aspect, the motor and the motor driving inverter play the roles of a boost PFC, a current regulator, or both.

Abstract: A direct current (DC)-DC converter includes a first port at a primary side of a transformer including a primary-side converter with primary-side switches and a second port at a secondary side including a second port converter with second-port switches and a resonant circuit including a first inductor, a capacitor, and a second inductor in LCL-T arrangement. A third port at the secondary side includes a third port converter with third-port switches. A controller controls the primary-side switches, the second-port switches, and the third-port switches at fixed-frequency for operation in a first mode, in which the first port supplies power to the second port and the third port, in a second mode, in which the second port supplies power to the first port and the third port, or in a third mode, in which the second port supplies power to the third port while the first port is disconnected.

Abstract: A novel phase-shift based modulation strategy is disclosed that enables a DC-DC converter to operate with zero voltage-switching (ZVS) across wide voltage and power range. The converter operates at a fixed fundamental frequency, with the output current controlled based on an amount of phase shift of the fundamental component at the output of an inverter portion of the converter. To achieve soft switching a rectifier portion of the converter is controlled to phase shift the fundamental component of the rectifier voltage observed at a rectifier reference terminal. More specifically, by requiring a phase shift of the voltage at the rectifier terminal relative to the output voltage of the inverter, the inverter current is such that ZVS is achieved. A converter and method are provided to implement DC-DC conversion with soft switching.

Abstract: A system for performing peak current mitigation in an application programming subsystem (APSS) dynamically performs mitigation based at least in part on power rail voltage and leakage current obtained at boot time. The voltage and leakage current obtained at boot time are used to estimate peak current. A map that is generated prior to boot time maps estimated peak current to throttling level and dictates different levels of throttling to be performed for different ranges of estimated peak current. At boot time, the map is used to map the estimated peak current to a level of throttling to be applied. If conditions at run time indicate that peak current is occurring or is likely to occur soon, the mapped level of throttling is applied to mitigate the peak current.

Abstract: The present disclosure provides a motor drive integrated on-board charger to reduce the quantity of components in an electric system of an electric vehicle. Reduction of components is achieved by utilizing the motor and the motor driving inverter as a part of the on-board charger in the charging mode. By controlling relays, electrical connections of the system may be reconfigured according to its mode of operation. In one aspect, the motor and the motor driving inverter play the roles of a boost PFC, a current regulator, or both.

Abstract: A magnetic component for a galvanically isolated LCL-T resonant converter is provided. The magnetic component includes first and second cores, a primary winding and a secondary winding. The first core includes a first outer post, a second outer post, and a center post. The primary winding has primary turns including first primary turns located around the first outer post and second primary turns located around the second outer post. The secondary winding has secondary turns including first secondary turns located around the first outer post and second secondary turns located around the second outer post. The center post of the first core and the second core are separated by a first air gap. The turns distribution and the first air gap are used to control and integrate a controllable leakage inductance, where the center post is used as a leakage path.

Abstract: The present disclosure provides a motor drive integrated on-board charger to reduce the quantity of components in an electric system of an electric vehicle. Reduction of components is achieved by utilizing the motor and the motor driving inverter as a part of the on-board charger in the charging mode. By controlling relays, electrical connections of the system may be reconfigured according to its mode of operation. In one aspect, the motor and the motor driving inverter play the roles of a boost PFC, a current regulator, or both.

Abstract: FCML rectifiers and control methods thereof are provided. The FCML rectifier operates with an input voltage and includes an inductor, a plurality of upper switches, and a plurality of lower switches. The upper and lower switches are electrically connected in series. The inductor is coupled between the input voltage and a midpoint between the upper switches and the lower switches. During critical transition points, at least one of first and second modulation schemes is performed. In the first modulation scheme, any rising edge of the control signal of any one lower switch is controlled to be synchronous with a rising edge of the control signal of at least one another lower switch for achieving ZVS. In the second modulation scheme, a phase-shift of the control signals and a switching frequency are controlled to achieve ZVS with minimum conduction loss.

Abstract: A novel phase-shift based modulation strategy is disclosed that enables a DC-DC converter to operate with zero voltage-switching (ZVS) across wide voltage and power range. The converter operates at a fixed fundamental frequency, with the output current controlled based on an amount of phase shift of the fundamental component at the output of an inverter portion of the converter. To achieve soft switching a rectifier portion of the converter is controlled to phase shift the fundamental component of the rectifier voltage observed at a rectifier reference terminal. More specifically, by requiring a phase shift of the voltage at the rectifier terminal relative to the output voltage of the inverter, the inverter current is such that ZVS is achieved. A converter and method are provided to implement DC-DC conversion with soft switching.

Abstract: Various embodiments of the present disclosure relate to power conversion using a planar transformer assembly that provides medium-voltage isolation at high frequencies. A planar transformer comprises primary and secondary planar windings configured to generate an isolated output. Each primary and secondary winding is interleaved on layers of a printed circuit board using one or more vias within the layers of the printed circuit board. The planar transformer also comprises a magnetic core and a field-shaping apparatus coupled with the printed circuit board. The field-shaping apparatus is configured to shape an electric field generated by the windings. The primary windings can be coupled to a DC source via switching devices while the secondary windings can be coupled via switching devices to one or more DC ports followed by AC inverters configured to generate three single-phase AC outputs for medium voltage applications.

Abstract: Aborting a cache memory flush may include initiating a flush operation in which a plurality of cache lines are flushed from a cache memory associated with a processor core that is entering a power collapse mode. Assertion of a wake-up signal associated with the processor core entering the power collapse mode may be detected. The wake-up signal may occur before completion of the flush operation. The flush operation may cease or abort in response to detecting the wake-up signal.

Abstract: Systems, methods, and computer programs are disclosed for managing memory channel connectivity. One embodiment of a system comprises a high-bandwidth memory client, a low-bandwidth memory client, and an address translator. The high-bandwidth memory client is electrically coupled to each of a plurality of memory channels via an interconnect. The low-bandwidth memory client is electrically coupled to only a portion of the plurality of memory channels via the interconnect. The address translator is in communication with the high-bandwidth memory client and configured to perform physical address manipulation when a memory page to be accessed by the high-bandwidth memory client is shared with the low-bandwidth memory client.

Abstract: Systems, methods, and computer programs are disclosed for dynamically adjusting memory channel interleave granularity. An embodiment of a system comprises a plurality of memory clients, a memory management unit (MMU), and an address translator. The plurality of memory clients are electrically coupled to each of a plurality of memory channels via an interconnect. The MMU is configured to receive a request for a memory allocation request for one or more memory pages from one of the plurality of memory client and, in response, select one of a plurality of interleave granularities for the one or more memory pages. The address translator is configured to translate a physical address to interleave memory data associated with the one or more memory pages at the selected interleave granularity.

Abstract: Systems and methods for memory power management based on allocation policies of memory structures of a processing system include entering a low power state for the processing system. The low power state includes one or more of a first, second, or third low power modes. In the first low power mode, for a first group of memory structures, periphery circuitry and memory cores are power collapsed. In the second low power mode, for a second group of memory structures, periphery circuitry is power collapsed and a retention voltage is provided to memory cores. In the third low power mode, a third group of memory structures are placed in an active mode. The first group includes strictly inclusive private caches, the second group includes non-data private caches, and the third group includes dirty or exclusive caches.

Abstract: Systems, methods, and computer programs are disclosed for dynamically adjusting memory channel interleave granularity. An embodiment of a system comprises a plurality of memory clients, a memory management unit (MMU), and an address translator. The plurality of memory clients are electrically coupled to each of a plurality of memory channels via an interconnect. The MMU is configured to receive a request for a memory allocation request for one or more memory pages from one of the plurality of memory client and, in response, select one of a plurality of interleave granularities for the one or more memory pages. The address translator is configured to translate a physical address to interleave memory data associated with the one or more memory pages at the selected interleave granularity.

Abstract: Systems, methods, and computer programs are disclosed for managing memory channel connectivity. One embodiment of a system comprises a high-bandwidth memory client, a low-bandwidth memory client, and an address translator. The high-bandwidth memory client is electrically coupled to each of a plurality of memory channels via an interconnect. The low-bandwidth memory client is electrically coupled to only a portion of the plurality of memory channels via the interconnect. The address translator is in communication with the high-bandwidth memory client and configured to perform physical address manipulation when a memory page to be accessed by the high-bandwidth memory client is shared with the low-bandwidth memory client.

Abstract: Systems for a method for monolithic workload scheduling in a portable computing device (“PCD”) having a hypervisor are disclosed. An exemplary method comprises instantiating a primary virtual machine at a first exception level, wherein the primary virtual machine comprises a monolithic scheduler configured to allocate workloads within and between one or more guest virtual machines in response to one or more interrupts, instantiating a secure virtual machine at the first exception level and instantiating one or more guest virtual machines at the first exception level as well. When an interrupt is received at a hypervisor associated with a second exception level, the interrupt is forwarded to the monolithic scheduler along with hardware usage state data and guest virtual machine usage state data. The monolithic scheduler may, in turn, generate one or more context switches which may comprise at least one intra-VM context switch and at least one inter-VM context switch.

Abstract: Disclosed is a method for protecting virtual machine data at a peripheral subsystem connected to at least one processor configured to host a plurality of virtual machines. In the method, context information, including a virtual machine identifier (VMID), is received. The VMID is unique to one of the plurality of virtual machines. A storage bank of a plurality of storage banks is selected based on the VMID included in the received context information. Each storage bank of the plurality of storage banks uses a same bus address range. A data bus is connected to the selected storage bank.

Abstract: A method and system for reducing power consumption while improving efficiency of a memory management unit of a portable computing device are described. The method and system include determining if data of a memory request exists within a first memory element external to the memory management unit. The first memory element may include a cache. If the data of the memory request does not exist within the first memory element, then a magnitude of a burst length value of the memory request may be determined. Subsequently, a page table walk may be conducted with a second memory element, such as DDR memory, that corresponds with the magnitude of the burst length value of the memory request. Each memory request may include a descriptor. The descriptor may have a reserved field region that includes a pre-fetch hint which indicates whether next descriptors in the second memory element are valid or not.

Abstract: A method and system for reducing power consumption while improving efficiency of a memory management unit of a portable computing device include determining if data of a memory request exists within a first memory element external to the memory management unit. The first memory element may include a cache. If the data of the memory request does not exist within the first memory element, then a magnitude of a burst length value of the memory request may be determined. Subsequently, a page table walk may be conducted with a second memory element, such as DDR (double-data rate) memory, that corresponds with the magnitude of the burst length value of second memory element (DDR). Each memory request may include a descriptor. The descriptor may have a reserved field region that includes a pre-fetch hint which indicates whether next descriptors in the second memory element are valid or not.