Patents by Inventor Satyan G. Pitroda

Satyan G. Pitroda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4154988
    Abstract: A method and means for providing a remote data station with access to the program memory of a stored program common control telecommunications switching system. The control complex has an input/output port and a modem for interfacing that port with its switching network. The control has the capability of setting up connections in the network between the modem and a selected trunk. Incoming connections to the modem are given only limited access to the stored program control, that access for the purpose of analyzing incoming data to detect a predetermined code. In the event the predetermined code is detected, the incoming connection is taken down, and an outgoing connection established to a distant station by dialing the number of an authorized station which is stored in the program memory. Full access to the program memory is then allowed, such that full access is provided only to stations whose telephone numbers are stored in the memory of the switching exchange.
    Type: Grant
    Filed: October 21, 1977
    Date of Patent: May 15, 1979
    Assignee: Wescom Switching, Inc.
    Inventors: William A. Fechalos, Byung C. Min, Satyan G. Pitroda, Carl J. Stehman
  • Patent number: 4149038
    Abstract: An idle channel test is provided for a digital time division multiplex and time switching network telecommunications system to detect and diagnose faults in an information path which routes digital information in dedicated channel time slots to and from a "time" switching network. In order to detect and diagnose faults in the information path which includes multiplex/demultiplex circuitry, an idle channel is selected as a test channel at the input to the multiplexer which in turn is the input to the switching network, a test pattern including a bit pattern and a parity bit is inserted into the test channel, the test pattern is connected via the switching network back to one of the demultiplexers and the bit pattern and parity bit are monitored for errors.
    Type: Grant
    Filed: May 15, 1978
    Date of Patent: April 10, 1979
    Assignee: Wescom Switching, Inc.
    Inventors: Satyan G. Pitroda, Byung C. Min, Tej N. Chaddha
  • Patent number: 4146749
    Abstract: In a telecommunications switching system having an "all time" network, the network is divided into a plurality of blocks, each of the blocks having assigned thereto dedicated groups of access ports for completing connections between those ports and any of the other ports in the system. A single spare network block is provided having a programmable identity and capable of functioning in the place of any of the primary blocks. In the event of a malfunction in a primary block, the spare network block is assigned the identity of the primary block, is enabled, the faulty block disabled, and call processing continues just as if the primary block were on line.
    Type: Grant
    Filed: September 16, 1977
    Date of Patent: March 27, 1979
    Assignee: Wescom Switching, Inc.
    Inventors: Bernard J. Pepping, Satyan G. Pitroda, Byung C. Min
  • Patent number: 4031328
    Abstract: A conference arrangement for use in pulse code modulated telecommunication systems including first and second control memories and a comparison logic circuit. Two words corresponding to two channels are read from information memory during each time slot and after proper comparison, the largest sample is transmitted to a third channel.
    Type: Grant
    Filed: September 18, 1975
    Date of Patent: June 21, 1977
    Assignee: GTE Automatic Electric Laboratories Incorporated
    Inventor: Satyan G. Pitroda
  • Patent number: 4022991
    Abstract: A conference arrangement for use in a pulse code modulated system including first and second control memories and a comparison logic circuit. Two words corresponding to two channels are read from information memory during each time slot and after proper comparison, the largest sample is transmitted to a third channel. Also included is a dial tone source for supplying dial tone to all terminations in the system by writing a time slot number assigned to the dial tone source and the respective ones of the channel memory words in the control memory associated with the channels.
    Type: Grant
    Filed: September 18, 1975
    Date of Patent: May 10, 1977
    Assignee: GTE Automatic Electric Laboratories Incorporated
    Inventors: Michael J. Kelly, Alex W. Kobylar, Robert L. Lindsay, Satyan G. Pitroda, Charles J. Simon
  • Patent number: 3999050
    Abstract: An electronic diary having combined clock-calendar means and diary storage means is provided wherein a random access memory is employed in a diary mode of operation for the storage and readout of preselected daily schedule and message events keyed for visual display in response to equal time comparisons with real time of day TOD as generated by the clock-calendar means. The electronic diary is capable of being added to present state-of-the-art electronic calculators for facilitating economy of parts through commonality of keyboard, power supply and visual display features. The electronic diary is comprised of a keyboard selector panel, power supply means, a message storage and control unit, a clock and calendar unit, display control logic, time comparison logic, audible alarm, and visual display means. Optionally, the electronic diary is comprised of a keyboard selector panel, power supply means, memory, micro-processor circuit, and visual display means.
    Type: Grant
    Filed: October 10, 1975
    Date of Patent: December 21, 1976
    Inventor: Satyan G. Pitroda
  • Patent number: 3997874
    Abstract: Switching apparatus is disclosed having a time divided switching network for use in switching time division multiplexed channels employing PCM codes. The network employs two data memories for selectively storing received PCM codes in locations associated with specific transmission channels. These memories are addressed alternately by sequential addressing apparatus and additional memory apparatus which store selected addressing codes. These addressing codes are determined by a control unit to effect shifts in the channel assignments of respective codes by selectively transferring such codes between the data memories, thereby effecting the necessary time divided connections.
    Type: Grant
    Filed: September 24, 1975
    Date of Patent: December 14, 1976
    Assignee: GTE Automatic Electric Laboratories Incorporated
    Inventors: Michael J. Kelly, Alex W. Kobylar, Satyan G. Pitroda
  • Patent number: 3959588
    Abstract: A digital line synchronizer system for use with a digital PCM TDM switching exchange will provide a vector address off-set between the address locations of WRITE and READ vectors within a multiple frame input buffer memory bank of the incoming line equipment upon the occurrence of either a loss of receive framing synchronization or the equalization of time reference between the WRITE and READ vectors with respect to the input buffer memory bank. The vector address off-set is provided to prevent the condition of information distortion due to the phenomenon of vector slippage whereby a given channel/word slot within the multiple frame memory bank is twice written with incoming PCM data under the operation of the WRITE vector address before the first stored sample of PCM data can be retrieved via the use of the READ vector address.
    Type: Grant
    Filed: May 5, 1975
    Date of Patent: May 25, 1976
    Assignee: GTE Automatic Electric Laboratories Incorporated
    Inventors: Michael J. Kelly, Satyan G. Pitroda