Patents by Inventor Satyanarayana Lakshmipathi Billa

Satyanarayana Lakshmipathi Billa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9544402
    Abstract: A multi-rule approach for encoding rules grouped in a rule chunk is provided. The approach includes a multi-rule with a multi-rule header representing headers of the rules and, in some cases, dimensional data representing dimensional data of the rules. The approach further includes disabling dimension matching of always matching dimensions, responding to an always match rule with a match response without matching, interleaving minimum/maximum values in a range field, interleaving value/mask values in a mask field, and for a given rule of rule chunk, encoding a priority field at the end of dimension data stored for the rule in the multi-rule. Advantageously, this approach provides efficient storage of rules and enables the efficient comparison of rules to keys.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: January 10, 2017
    Assignee: CAVIUM, INC.
    Inventors: Frank Worrell, Rajan Goyal, Satyanarayana Lakshmipathi Billa
  • Patent number: 9531690
    Abstract: A method, and corresponding apparatus, of managing processing thread migrations within a plurality of memory clusters, includes embedding, in memory components of the plurality of memory clusters, instructions indicative of processing thread migrations; storing, in one or more memory components of a particular memory cluster among the plurality of memory clusters, data configured to designate the particular memory cluster as a sink memory cluster, the sink memory cluster preventing an incoming migrated processing thread from migrating out of the sink memory cluster; and processing one or more processing threads, in one or more of the plurality of memory clusters, in accordance with at least one of the embedded migration instructions and the data stored in the one or more memory components of the sink memory cluster.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: December 27, 2016
    Assignee: Cavium, Inc.
    Inventors: Najeeb I. Ansari, Gregg A. Bouchard, Rajan Goyal, Jeffrey A. Pangborn, Satyanarayana Lakshmipathi Billa
  • Patent number: 9514246
    Abstract: A method and apparatus relate to recognizing anchored patterns from an input stream. Patterns from a plurality of given patterns are marked as anchored patterns. An anchored state tree for the anchored patterns of the plurality of given patterns is built, including nodes representing a state of the anchored state tree. For each node of the anchored state tree, a failure value equivalent to a node representing a state in an unanchored state tree representing unanchored patterns of the plurality of given patterns is determined.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: December 6, 2016
    Assignee: Cavium, Inc.
    Inventors: Satyanarayana Lakshmipathi Billa, Rajan Goyal
  • Patent number: 9507563
    Abstract: In one embodiment, a method of walking a non-deterministic finite automata (NFA) graph representing a pattern includes extracting a node type and an element from a node of the NFA graph. The method further includes matching a segment of a payload for the element by matching the payload for the element at least zero times, the number of times based on the node type.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: November 29, 2016
    Assignee: Cavium, Inc.
    Inventors: Satyanarayana Lakshmipathi Billa, Rajan Goyal
  • Patent number: 9438561
    Abstract: Nodes of a per-pattern NFA may be stored amongst one or more of a plurality of memories based on a node distribution determined as a function of hierarchical levels mapped to the plurality of memories and per-pattern NFA storage allocation settings configured for the hierarchical levels. At least one processor may be configured to cache one or more nodes of the per-pattern NFA in the node cache based on a cache miss of a given node of the one or more nodes and a hierarchical node transaction size associated with a given hierarchical level mapped to a given memory in which the given node is stored, optimizing run time performance of the walk.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: September 6, 2016
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa, Abhishek Dikshit
  • Patent number: 9430511
    Abstract: In an embodiment, a method of updating a memory with a plurality of memory lines, the memory storing a tree, a plurality of buckets, and a plurality of rules, includes maintaining a copy of the memory with a plurality of memory lines. The method further includes writing a plurality of changes to at least one of the tree, the plurality of buckets, and the plurality of rules to the copy. The method further includes determining whether each of the plurality of changes is an independent write or a dependent write. The method further includes merging independent writes to the same line of the copy. The method further includes transferring updates from the plurality of lines of the copy to the plurality of lines of the memory.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: August 30, 2016
    Assignee: Cavium, Inc.
    Inventors: Satyanarayana Lakshmipathi Billa, Rajan Goyal
  • Patent number: 9426166
    Abstract: A method and corresponding apparatus for run time processing use a Deterministic Finite Automata (DFA) and Non-Deterministic Finite Automata (NFA) to find the existence of a pattern in a payload. A subpattern may be selected from each pattern in a set of one or more regular expression patterns based on at least one heuristic. The DFA may be generated from selected subpatterns from all patterns in the set, and at least one NFA may be generated for at least one pattern in the set, optimizing run time performance of the run time processing.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: August 23, 2016
    Assignee: Cavium, Inc.
    Inventors: Satyanarayana Lakshmipathi Billa, Rajan Goyal
  • Patent number: 9426165
    Abstract: A method and corresponding apparatus are provided implementing run time processing using Deterministic Finite Automata (DFA) and Non-Deterministic Finite Automata (NFA) to find the existence of a pattern in a payload. A subpattern may be selected from each pattern in a set of one or more regular expression patterns based on at least one heuristic and a unified deterministic finite automata (DFA) may be generated using the subpatterns selected from all patterns in the set, and at least one non-deterministic finite automata (NFA) may be generated for at least one pattern in the set, optimizing run time performance of the run time processing.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: August 23, 2016
    Assignee: Cavium, Inc.
    Inventors: Satyanarayana Lakshmipathi Billa, Rajan Goyal, Abhishek Dikshit
  • Patent number: 9419943
    Abstract: A method, and corresponding apparatus and system are provided for optimizing matching at least one regular expression pattern in an input stream by walking at least one finite automaton in a speculative manner. The speculative manner may include walking at least two nodes of a given finite automaton, of the at least one finite automaton, in parallel, with a segment, at a given offset within a payload of a packet in the input stream. The walking may include determining a match result for the segment, at the given offset within the payload, at each node of the at least two nodes. The walking may further include determining at least one subsequent action for walking the given finite automaton, based on an aggregation of each match result determined.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: August 16, 2016
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa, Abhishek Dikshit
  • Publication number: 20160070818
    Abstract: A method and apparatus relate to recognizing anchored patterns from an input stream. Patterns from a plurality of given patterns are marked as anchored patterns. An anchored state tree for the anchored patterns of the plurality of given patterns is built, including nodes representing a state of the anchored state tree. For each node of the anchored state tree, a failure value equivalent to a node representing a state in an unanchored state tree representing unanchored patterns of the plurality of given patterns is determined.
    Type: Application
    Filed: February 26, 2015
    Publication date: March 10, 2016
    Inventors: Satyanarayana Lakshmipathi Billa, Rajan Goyal
  • Publication number: 20160021060
    Abstract: In a processor of a security appliance, an input of a sequence of characters is walked through a finite automata graph generated for at least one given pattern. At a marked node of the finite automata graph, if a specific type of the at least one given pattern is matched at the marked node, the input sequence of characters is processed through a reverse non-deterministic finite automata (rNFA) graph generated for the specific type of the at least one given pattern by walking the input sequence of characters backwards through the rNFA beginning from an offset of the input sequence of characters associated with the marked node. Generating the rNFA for a given pattern includes inserting processing nodes for processing an input sequence of patterns to determine a match for the given pattern. In addition, the rNFA is generated from the given type of pattern.
    Type: Application
    Filed: September 24, 2015
    Publication date: January 21, 2016
    Inventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa
  • Publication number: 20160021123
    Abstract: In a processor of a security appliance, an input of a sequence of characters is walked through a finite automata graph generated for at least one given pattern. At a marked node of the finite automata graph, if a specific type of the at least one given pattern is matched at the marked node, the input sequence of characters is processed through a reverse non-deterministic finite automata (rNFA) graph generated for the specific type of the at least one given pattern by walking the input sequence of characters backwards through the rNFA beginning from an offset of the input sequence of characters associated with the marked node. Generating the rNFA for a given pattern includes inserting processing nodes for processing an input sequence of patterns to determine a match for the given pattern. In addition, the rNFA is generated from the given type of pattern.
    Type: Application
    Filed: September 24, 2015
    Publication date: January 21, 2016
    Inventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa
  • Patent number: 9208438
    Abstract: A packet classification system, apparatus, and corresponding apparatus are provided for enabling packet classification. A processor of a security appliance coupled to a network uses a classifier table having a plurality of rules, the plurality of rules having at least one field, to build a decision tree structure for packet classification. Duplication in the decision tree may be identified, producing a wider, shallower decision tree that may result in shorter search times with reduced memory requirements for storing the decision tree. A number of operations needed to identify duplication in the decision tree may be reduced, thereby increasing speed and efficiency of a compiler building the decision tree.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 8, 2015
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Kenneth A. Bullis, Satyanarayana Lakshmipathi Billa
  • Patent number: 9203805
    Abstract: In a processor of a security appliance, an input of a sequence of characters is walked through a finite automata graph generated for at least one given pattern. At a marked node of the finite automata graph, if a specific type of the at least one given pattern is matched at the marked node, the input sequence of characters is processed through a reverse non-deterministic finite automata (rNFA) graph generated for the specific type of the at least one given pattern by walking the input sequence of characters backwards through the rNFA beginning from an offset of the input sequence of characters associated with the marked node. Generating the rNFA for a given pattern includes inserting processing nodes for processing an input sequence of patterns to determine a match for the given pattern. In addition, the rNFA is generated from the given type of pattern.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: December 1, 2015
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa
  • Patent number: 9191321
    Abstract: A packet classification system, methods, and corresponding apparatus are provided for enabling packet classification. A processor of a security appliance coupled to a network uses a classifier table having a plurality of rules, the plurality of rules having at least one field, to build a decision tree structure including a plurality of nodes, the plurality of nodes including a subset of the plurality of rules. The methods may produce wider, shallower trees that result in shorter search times and reduced memory requirements for storing the trees.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: November 17, 2015
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Kenneth A. Bullis, Satyanarayana Lakshmipathi Billa
  • Publication number: 20150295889
    Abstract: At least one per-pattern non-deterministic finite automaton (NFA) may be generated for a single regular expression pattern and may include a respective set of nodes. Nodes of the respective set of nodes of each per-pattern NFA generated may be distributed for storing in a plurality of memories based on hierarchical levels mapped to the plurality of memories and per-pattern NFA storage allocation settings configured for the hierarchical levels, optimizing run time performance for matching regular expression patterns in an input stream.
    Type: Application
    Filed: April 14, 2014
    Publication date: October 15, 2015
    Applicant: Cavium, Inc.
    Inventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa
  • Publication number: 20150295891
    Abstract: Nodes of a per-pattern NFA may be stored amongst one or more of a plurality of memories based on a node distribution determined as a function of hierarchical levels mapped to the plurality of memories and per-pattern NFA storage allocation settings configured for the hierarchical levels. At least one processor may be configured to cache one or more nodes of the per-pattern NFA in the node cache based on a cache miss of a given node of the one or more nodes and a hierarchical node transaction size associated with a given hierarchical level mapped to a given memory in which the given node is stored, optimizing run time performance of the walk.
    Type: Application
    Filed: April 14, 2014
    Publication date: October 15, 2015
    Applicant: Cavium, Inc.
    Inventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa, Abhishek Dikshit
  • Publication number: 20150293846
    Abstract: At least one processor may be operatively coupled to a plurality of memories and a node cache and configured to walk nodes of a per-pattern non-deterministic finite automaton (NFA). Nodes of the per-pattern NFA may be stored amongst one or more of the plurality of memories based on a node distribution determined as a function of hierarchical levels mapped to the plurality of memories and per-pattern NFA storage allocation settings configured for the hierarchical levels, optimizing run time performance of the walk.
    Type: Application
    Filed: April 14, 2014
    Publication date: October 15, 2015
    Applicant: Cavium, Inc.
    Inventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa
  • Patent number: 9137340
    Abstract: A system, apparatus, and method are provided for adding, deleting, and modifying rules in one update from the perspective of an active search process for packet classification. While a search processor searches for one or more rules that match keys generated from received packets, there is a need to add, delete, or modify rules. By adding, deleting, and modifying rules in one update from the perspective of an active search process for packet classification, performance and functionality of the active search process may be maintained, thereby preventing packet loss and preserving throughput.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: September 15, 2015
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Kenneth A. Bullis, Satyanarayana Lakshmipathi Billa
  • Publication number: 20150220454
    Abstract: A method, and corresponding apparatus and system are provided for optimizing matching of at least one regular expression pattern in an input stream by storing a context for walking a given node, of a plurality of nodes of a given finite automaton of at least one finite automaton, the store including a store determination, based on context state information associated with a first memory, for accessing the first memory and not a second memory or the first memory and the second memory. Further, to retrieve a pending context, the retrieval may include a retrieve determination, based on the context state information associated with the first memory, for accessing the first memory and not the second memory or the second memory and not the first memory. The first memory may have read and write access times that are faster relative to the second memory.
    Type: Application
    Filed: January 31, 2014
    Publication date: August 6, 2015
    Applicant: Cavium, Inc.
    Inventors: Rajan Goyal, Satyanarayana Lakshmipathi Billa