Abstract: A smart block control method, system, and computer program product, include capturing an intent of using one or more smart blocks and a domain of the smart blocks, determining an order of each of the smart blocks relative to each other, calculating an accuracy of a determined order of the smart blocks compared with the intent, and outputting an instruction via the one or more the smart blocks, in response to said calculating the accuracy of the determined order of the smart blocks compared with the predetermined order of the smart blocks.

Abstract: Techniques are provided that facilitate adaptively expanding vocabulary of an entity. A computer-implemented method is provided that comprises determining, by a device operatively coupled to a processor, one or more areas of a word relationship graph that correspond to a zone of proximal vocabulary development of an entity based on one or more seed words included in a vocabulary associated with the entity. The computer-implemented method can further comprise, identifying, by the device, a set of words included the word relationship graph based on respective words in the set being associated with the one or more areas, and selecting, by the device, a subset of recommended words for learning by the entity from the set of words based on one or more criteria.

Abstract: Techniques are provided that facilitate adaptively expanding vocabulary of an entity. A computer-implemented method is provided that comprises determining, by a device operatively coupled to a processor, one or more areas of a word relationship graph that correspond to a zone of proximal vocabulary development of an entity based on one or more seed words included in a vocabulary associated with the entity. The computer-implemented method can further comprise, identifying, by the device, a set of words included the word relationship graph based on respective words in the set being associated with the one or more areas, and selecting, by the device, a subset of recommended words for learning by the entity from the set of words based on one or more criteria.

Abstract: A smart block control method, system, and computer program product, include capturing an intent of using one or more smart blocks and a domain of the smart blocks, determining an order of each of the smart blocks relative to each other, calculating an accuracy of a determined order of the smart blocks compared with the intent, and outputting an instruction via the one or more the smart blocks, in response to said calculating the accuracy of the determined order of the smart blocks compared with the predetermined order of the smart blocks.

Abstract: An in-situ process is described incorporating plasma enhanced chemical vapor deposition comprising flowing at least one of a Si, Si+C, B, Si+B, Si+B+C, and B+C containing precursor, and a N containing precursors at first times and removing the N precursor at second times and starting the flow of an oxidant gas and a porogen gas into the chamber. A dielectric layer is described comprising a network having inorganic random three dimensional covalent bonding throughout the network which contains at least one SiCN, SiCNH, SiN, SiNH, BN, BNH, CBN, CBNH, BSiN, BSiNH, SiCBN and SiCBNH as a first component and a low k dielectric as a second component adjacent thereto.

Abstract: A structure and method to produce an airgap on a substrate having a dielectric layer and copper interconnects with sublithographic perforations therein which are ordered throughout the wafer structure in a macro level and a micro level with no change in order orientation and the top layer of the copper interconnects are not exposed.

Abstract: An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like.

Abstract: Disclosed is a process of an integration method to form an air gap in an interconnect. On top of a metal wiring layer on a semiconductor substrate is deposited a dielectric cap layer followed by a sacrificial dielectric layer and pattern transfer layers. A pattern is transferred through the pattern transfer layers, sacrificial dielectric layer, dielectric cap layer and into the metal wiring layer. The presence of the sacrificial dielectric layer aids in controlling the thickness and profile of the dielectric cap layer which in turn affects reliability of the interconnect.

Abstract: An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like.

Abstract: Interconnect structures are fabricated by methods that comprise depositing a thin conformal passivation dielectric and/or diffusion barrier cap and/or hard mask by an atomic layer deposition or supercritical fluid based process.

Abstract: A structure and method to produce an airgap on a substrate having a dielectric layer with a pattern transferred onto the dielectric layer and a self aligned block out mask transferred on the dielectric layer around the pattern.

Abstract: A process for preparing an electronics structure involves coating a substrate stack with a sacrificial multilayer hardmask stack, developing a pattern in a resist layer coated on a topmost layer of the multilayer hardmask stack, transferring the pattern into the hardmask stack, blocking a portion of the pattern, and then transferring an unblocked portion of the pattern into the substrate stack. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader quickly to ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the appended issued claims.

Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

Abstract: A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics.

Abstract: A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics.

Abstract: A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics.

Abstract: The present invention relates to formation of air gaps in metal/insulator interconnect structures, and to the use of supercritical fluid (SCF)-based methods to extract sacrificial place-holding materials to form air gaps in a structure. Supercritical fluids have gas-like diffusivities and viscosities, and very low or zero surface tension, so SCF's can penetrate small access holes and/or pores in a perforated or porous bridge layer to reach the sacrificial material. Examples of SCFs include CO2 (with or without cosolvents or additives) and ethylene (with or without cosolvents or additives). In a more general embodiment, SCF-based methods for forming at least partially enclosed air gaps in structures that are not interconnect structures are disclosed.