Abstract: An integrated circuit copper interconnect structure is formed by forming a dielectric layer (90) over a semiconductor substrate (10). Trenches (110) and vias (120) are formed in the dielectric layer (90) and a barrier layer (130) is formed in the trenches (110) and vias (120) using material such as iridium, iridium oxide, ruthenium, ruthenium oxide, rhodium, rhodium oxide, rhenium, rhenium oxide, platinum, platinum oxide, palladium and palladium oxide. Copper (147) is then used to fill the remaining area in the trenches (110) and vias (120).

Abstract: An embodiment of the invention is a method of manufacturing an integrated circuit. The method includes forming a capping layer of a back end structure (step 706), drilling an extraction line from the capping layer to an inter-metal dielectric layer (step 708), performing a supercritical fluid process to remove portions of the inter-metal dielectric layer that are coupled to the extraction line (step 710): thereby forming a denuded dielectric region. Another embodiment of the invention is an integrated circuit 2 having a back-end structure 5 coupled to a front-end structure 4. The back-end structure 5 having a first metal level 22. The first metal level 22 having metal interconnects 15 and an inter-metal dielectric layer 19. The back-end structure 5 further containing an extraction line 24 and a denuded dielectric region 25 coupled to the extraction line 24.

Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and includes surface protection cladding (109) for the copper metal (104b) of the top metal interconnect.

Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (104) is integrated at the top metal interconnect level (104) and may be implemented with only one additional masking layer. The decoupling capacitor (106) is formed on a copper interconnect line (104a). An aluminum cap layer (118) provides electrical connection to the top electrode (112) of the decoupling capacitor (106).

Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and includes surface protection layer (109) for the copper metal (104b) of the top metal interconnect.

Abstract: A stacked interconnect structure to connect a first layer copper line with a second layer copper line and method of making the same includes depositing a barrier layer over the inner surfaces of a via extending through a first dielectric layer between the first and second layer copper lines. The first barrier layer provides a barrier to copper diffusion into the dielectric layer. The first barrier layer is then selectively etched from the bottom surface of the via, after which a second barrier layer is deposited over the vertical and bottom surfaces of the via. The second barrier layer also provides a barrier to the diffusion of copper, but is less resistive than the first barrier, and ensure wettability of the copper.

Abstract: A Low K dielectric layer (20) is formed over a semiconductor (10). Trenches (110, 120) are formed in the dielectric layer (2) and a barrier layer (70) is formed in the trenches. The barrier layer has a thickness of X1 over the upper surface of the dielectric layer and X2 on the sidewalls of the trenches where X1 is greater than X2. A second barrier layer (130) can be formed over the first barrier layer (70) and copper (100) is formed over both barrier layers to fill the trench.

Abstract: An embodiment of the invention is a capacitor comprising a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, sidewalls 105, and a top electrode 110 coupled to a second interconnect 30b of the top metal level 10. Another embodiment of the invention is a method of manufacturing a capacitor using a first mask 140 to form a material stack that includes a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, and a partial top electrode 100. The method further includes using a second mask 150 to form a complete top electrode coupled to a second interconnect 30b of the top metal level 10.

Abstract: An embodiment of the invention is a capacitor comprising a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, sidewalls 105, and a top electrode 110 coupled to a second interconnect 30b of the top metal level 10. Another embodiment of the invention is a method of manufacturing a capacitor using a first mask 140 to form a material stack that includes a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, and a partial top electrode 100. The method further includes using a second mask 150 to form a complete top electrode coupled to a second interconnect 30b of the top metal level 10.

Abstract: A trench (70) is formed in a dielectric layer (20). A first metal layer (80) is formed in the trench using physical vapor deposition. A second metal layer (100) is formed in the trench (70) over the first metal layer (80) using chemical vapor deposition. Copper (110) is used to fill the trench (70) by electroplating copper directly onto the second metal (100).

Abstract: A system (25) for detecting defects in a semiconductor wafer (10), such defects including voids (V) present in metal conductors (2, 4) and plugs (7), is disclosed. An x-ray source (20) irradiates the wafer (10) through a first aperture array (24) having openings (26); a second aperture array (28) is located on the opposite side of the wafer (10) from the source (20), and has openings (30) that are aligned and registered with the openings (26) in the first aperture array (24). An array of x-ray detectors (31) is located adjacent to the second aperture array (28), with each detector (31) associated with one of the openings (30) of the second aperture array (28). The detectors (31) communicate signals regarding the magnitude of x-ray energy that is transmitted through wafer (10) at locations defined by the openings (26, 30) through aperture arrays (24, 28), to an analysis computer (34). A wafer translation system (32) indexes or otherwise moves the wafer (10) between the aperture arrays (24, 28).

Abstract: A process for polishing a semiconductor wafer includes the steps of providing a plurality of wafers, forming a first layer, such as a barrier layer, over at least a portion of each wafer, and forming at least one layer including copper over at least a portion of each first layer. The process also includes the steps of providing a first polishing pad, providing a buffing pad, providing a plurality of operatively connected wafer carriers, and disposing a wafer within each of the wafer carriers. The process further includes the steps of disposing a first slurry composition on the first polishing pad and polishing a first wafer with the first polishing pad for a first length of time, in which the first polishing pad substantially removes the copper layer of the first wafer.

Abstract: A process for polishing a semiconductor wafer includes the steps of providing a plurality of wafers, forming a first layer, such as a barrier layer, over at least a portion of each wafer, and forming at least one layer including copper over at least a portion of each first layer. The process also includes the steps of providing a first polishing pad, providing a buffing pad, providing a plurality of operatively connected wafer carriers, and disposing a wafer within each of the wafer carriers. The process further includes the steps of disposing a first slurry composition on the first polishing pad and polishing a first wafer with the first polishing pad for a first length of time, in which the first polishing pad substantially removes the copper layer of the first wafer.