Patents by Inventor Satyavolu S. Papa Rao

Satyavolu S. Papa Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10269993
    Abstract: A photovoltaic device, such as a solar cell, including a copper-containing-grid metallization structure that contains a metal phosphorus layer as a diffusion barrier is provided. The copper-containing-grid metallization structure includes, from bottom to top, an electroplated metal phosphorus layer that does not include copper or a copper alloy located within a grid pattern formed on a front side surface of a semiconductor substrate, and an electroplated copper-containing layer. A method of forming such a structure is also provided.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: April 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kathryn C. Fisher, Qiang Huang, Satyavolu S. Papa Rao
  • Patent number: 10167443
    Abstract: A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution removes an etch residue that includes a majority of hydrocarbons and at least one element selected from the group consisting of carbon, oxygen, fluorine, nitrogen and silicon. In one example, the aqueous solution may be cerium ammonium nitrate (Ce(NH4)(NO3)),(CAN).
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: January 1, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ZEON CORPORATION
    Inventors: Robert L. Bruce, Sebastian U. Engelmann, Eric A. Joseph, Mahmoud Khojasteh, Masahiro Nakamura, Satyavolu S. Papa Rao, Bang N. To, George G. Totir, Yu Zhu
  • Patent number: 10170644
    Abstract: A photovoltaic device is provided that includes a semiconductor substrate including a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion one lying on top of the other, wherein an upper exposed surface of the semiconductor substrate represents a front side surface of the semiconductor substrate. A plurality of patterned antireflective coatings is located on the front side surface to provide a grid pattern including a busbar region and finger regions. The busbar region includes at least a real line interposed between at least two dummy lines. A material stack including at least one metal layer located on the semiconductor substrate in the busbar region and the finger regions.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kathryn C. Fisher, Qiang Huang, Satyavolu S. Papa Rao, David L. Rath
  • Patent number: 9786852
    Abstract: Embodiments of the invention include a method of fabrication of a semiconductor structure. The method of fabrication includes: Forming a trench in a first dielectric material down to a first conductive material of a bottom gate. A sidewall of the trench contacts a top surface of the first conductive material. Depositing a second conductive material on the sidewall of the trench, which forms an electrical connection with the first conductive material. Depositing a second dielectric material in the trench, and on the second conductive material. Depositing a gate dielectric material on the second conductive material and the dielectric materials. Forming a channel material on the gate dielectric material. Depositing another conductive material on the channel material and portions of the gate dielectric material to form a source terminal and a drain terminal.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Aaron D. Franklin, Shu-Jen Han, Satyavolu S. Papa Rao, Joshua T. Smith
  • Publication number: 20170200838
    Abstract: A photovoltaic device is provided that includes a semiconductor substrate including a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion one lying on top of the other, wherein an upper exposed surface of the semiconductor substrate represents a front side surface of the semiconductor substrate. A plurality of patterned antireflective coatings is located on the front side surface to provide a grid pattern including a busbar region and finger regions. The busbar region includes at least a real line interposed between at least two dummy lines. A material stack including at least one metal layer located on the semiconductor substrate in the busbar region and the finger regions.
    Type: Application
    Filed: March 27, 2017
    Publication date: July 13, 2017
    Inventors: Kathryn C. Fisher, Qiang Huang, Satyavolu S. Papa Rao, David L. Rath
  • Patent number: 9608134
    Abstract: A method of forming a photovoltaic device is provided that includes a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion, wherein an upper exposed surface of one of the semiconductor portions represents a front side surface of the semiconductor substrate. Patterned antireflective coating layers are formed on the front side surface of the semiconductor surface to provide a grid pattern including a busbar region and finger region. A mask having a shape that mimics each patterned antireflective coating layer is provided atop each patterned antireflective coating layer. A metal layer is electrodeposited on the busbar region and the finger regions. After removing the mask, an anneal is performed that reacts metal atoms from the metal layer react with semiconductor atoms from the busbar region and the finger regions forming a metal semiconductor alloy.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kathryn C. Fisher, Qiang Huang, Satyavolu S. Papa Rao, David L. Rath
  • Publication number: 20170044470
    Abstract: A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution removes an etch residue that includes a majority of hydrocarbons and at least one element selected from the group consisting of carbon, oxygen, fluorine, nitrogen and silicon. In one example, the aqueous solution may be cerium ammonium nitrate (Ce(NH4)(NO3)),(CAN).
    Type: Application
    Filed: October 26, 2016
    Publication date: February 16, 2017
    Inventors: Robert L. Bruce, Sebastian U. Engelmann, Eric A. Joseph, Mahmoud Khojasteh, Masahiro Nakamura, Satyavolu S. Papa Rao, Bang N. To, George G. Totir, Yu Zhu
  • Patent number: 9536731
    Abstract: A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution removes an etch residue that includes a majority of hydrocarbons and at least one element selected from the group consisting of carbon, oxygen, fluorine, nitrogen and silicon. In one example, the aqueous solution may be cerium ammonium nitrate (Ce(NH4)(NO3)),(CAN).
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: January 3, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ZEON CORPORATION
    Inventors: Robert L. Bruce, Sebastian U. Engelmann, Eric A. Joseph, Mahmoud Khojasteh, Masahiro Nakamura, Satyavolu S. Papa Rao, Bang N. To, George G. Totir, Yu Zhu
  • Publication number: 20160197208
    Abstract: A photovoltaic device, such as a solar cell, including a copper-containing-grid metallization structure that contains a metal phosphorus layer as a diffusion barrier is provided. The copper-containing-grid metallization structure includes, from bottom to top, an electroplated metal phosphorus layer that does not include copper or a copper alloy located within a grid pattern formed on a front side surface of a semiconductor substrate, and an electroplated copper-containing layer. A method of forming such a structure is also provided.
    Type: Application
    Filed: March 14, 2016
    Publication date: July 7, 2016
    Inventors: Kathryn C. Fisher, Qiang Huang, Satyavolu S. Papa Rao
  • Publication number: 20160087232
    Abstract: Embodiments of the invention include a method of fabrication of a semiconductor structure. The method of fabrication includes: Forming a trench in a first dielectric material down to a first conductive material of a bottom gate. A sidewall of the trench contacts a top surface of the first conductive material. Depositing a second conductive material on the sidewall of the trench, which forms an electrical connection with the first conductive material. Depositing a second dielectric material a in the trench, and on the second conductive material. Depositing a gate dielectric material on the second conductive material and the dielectric materials. Forming a channel material on the gate dielectric material. Depositing another conductive material on the channel material and portions of the gate dielectric material to form a source terminal and a drain terminal.
    Type: Application
    Filed: December 2, 2015
    Publication date: March 24, 2016
    Inventors: Aaron D. Franklin, Shu-Jen Han, Satyavolu S. Papa Rao, Joshua T. Smith
  • Patent number: 9284656
    Abstract: A photovoltaic device, such as a solar cell, including a copper-containing-grid metallization structure that contains a metal phosphorus layer as a diffusion barrier is provided. The copper-containing-grid metallization structure includes, from bottom to top, an electroplated metal phosphorus layer that does not include copper or a copper alloy located within a grid pattern formed on a front side surface of a semiconductor substrate, and an electroplated copper-containing layer. A method of forming such a structure is also provided.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: March 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kathryn C. Fisher, Qiang Huang, Satyavolu S. Papa Rao
  • Patent number: 9246112
    Abstract: Embodiments of the invention include a method of fabrication and a semiconductor structure. The method of fabrication includes depositing a first dielectric material on a substrate, and forming a bottom gate including filling a first opening in the first dielectric layer with a first conductive material. Next, depositing a second dielectric material, and forming a trench in the second dielectric material down to the first conductive material. Next, depositing a second conductive material on the sidewall of the trench forming an electrical connection between the first conductive material and the second conductive material, depositing a third dielectric material in the trench, and removing excess material not in the trench. Next, depositing a gate dielectric layer, and forming a channel layer of carbon nanotubes on the gate dielectric layer. Lastly, depositing a third conductive material on the channel layer forming source and drain terminals.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: January 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Aaron D. Franklin, Shu-Jen Han, Satyavolu S. Papa Rao, Joshua T. Smith
  • Patent number: 9246024
    Abstract: A photovoltaic device is provided that includes a semiconductor substrate including a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion one on top of the other. A plurality of patterned antireflective coating layers is located on a p-type semiconductor surface of the semiconductor substrate, wherein at least one portion of the p-type semiconductor surface of the semiconductor substrate is exposed. Aluminum is located directly on the at least one portion of the p-type semiconductor surface of the semiconductor substrate that is exposed.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: January 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kathryn C. Fisher, Qiang Huang, Satyavolu S. Papa Rao, Ming-Ling Yeh
  • Patent number: 9188578
    Abstract: An anti-retraction capping material is formed on a surface of a nanowire that is located upon a dielectric membrane. A gap is then formed into the anti-retraction capping material and nanowire forming first and second capped nanowire structures of a nanodevice. The nanodevice can be used for recognition tunneling measurements including, for example DNA sequencing. The anti-retraction capping material serves as a mobility barrier to pin, i.e., confine, a nanowire portion of each of the first and second capped nanowire structures in place, allowing long-term structural stability. In some embodiments, interelectrode leakage through solution during recognition tunneling measurements can be minimized.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 17, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yann A. N. Astier, Jingwei Bai, Satyavolu S. Papa Rao, Kathleen B. Reuter, Joshua T. Smith
  • Patent number: 9182369
    Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nanogap.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: November 10, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yann Astier, Jingwei Bai, Michael A. Guillorn, Satyavolu S. Papa Rao, Joshua T. Smith
  • Patent number: 9128078
    Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nanogap.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: September 8, 2015
    Assignee: International Business Machines Corporation
    Inventors: Yann Astier, Jingwei Bai, Michael A. Guillorn, Satyavolu S. Papa Rao, Joshua T. Smith
  • Patent number: 9097698
    Abstract: An anti-retraction capping material is formed on a surface of a nanowire that is located upon a dielectric membrane. A gap is then formed into the anti-retraction capping material and nanowire forming first and second capped nanowire structures of a nanodevice. The nanodevice can be used for recognition tunneling measurements including, for example DNA sequencing. The anti-retraction capping material serves as a mobility barrier to pin, i.e., confine, a nanowire portion of each of the first and second capped nanowire structures in place, allowing long-term structural stability. In some embodiments, interelectrode leakage through solution during recognition tunneling measurements can be minimized.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: August 4, 2015
    Assignee: International Business Machines Corporation
    Inventors: Yann A. N. Astier, Jingwei Bai, Satyavolu S. Papa Rao, Kathleen B. Reuter, Joshua T. Smith
  • Publication number: 20150194619
    Abstract: Embodiments of the invention include a method of fabrication and a semiconductor structure. The method of fabrication includes depositing a first dielectric material on a substrate, and forming a bottom gate comprising filling a first opening in the first dielectric layer with a first conductive material. Next, depositing a second dielectric material, and forming a trench in the second dielectric material down to the first conductive material. Next, depositing a second conductive material on the sidewall of the trench forming an electrical connection between the first conductive material and the second conductive material, depositing a third dielectric material in the trench, and removing excess material not in the trench. Next, depositing a gate dielectric layer, and forming a channel layer of carbon nanotubes on the gate dielectric layer. Lastly, depositing a third conductive material on the channel layer forming source and drain terminals.
    Type: Application
    Filed: January 8, 2014
    Publication date: July 9, 2015
    Applicant: International Business Machines Corporation
    Inventors: Aaron D. Franklin, Shu-Jen Han, Satyavolu S. Papa Rao, Joshua T. Smith
  • Publication number: 20150153320
    Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nano gap.
    Type: Application
    Filed: January 28, 2015
    Publication date: June 4, 2015
    Inventors: Yann Astier, Jingwei Bai, Michael A. Guillorn, Satyavolu S. Papa Rao, Joshua T. Smith
  • Publication number: 20150144888
    Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nanogap.
    Type: Application
    Filed: January 28, 2015
    Publication date: May 28, 2015
    Inventors: Yann Astier, Jingwei Bai, Michael A. Guillorn, Satyavolu S. Papa Rao, Joshua T. Smith