Patents by Inventor Satyavolu S. Papa Rao
Satyavolu S. Papa Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240165421Abstract: There is set forth herein: an implant adapted for implantation in a user having a neocortex at least part of which has been made responsive to light, the neocortex including a plurality of columns forming an array of cortical columns capable of description by a cortical map characterizing, identifying or defining a location or topographical relationship and placement for respective ones of the plurality of columns; wherein the implant includes an emitter array; wherein the emitter array includes a plurality of emitters, wherein respective ones of the plurality of emitters are configured to emit light toward the array of cortical columns.Type: ApplicationFiled: February 12, 2022Publication date: May 23, 2024Applicant: THE RESEARCH FOUNDATION FOR THE STATE UNIVERSITY OF NEW YORKInventors: Stephen L. MACKNIK, Susana MARTINEZ-CONDE, Edward WHITE, Satyavolu S. PAPA RAO, Spyridon GALIS, John N. CARTER, Olivya CABALLERO
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Patent number: 10269993Abstract: A photovoltaic device, such as a solar cell, including a copper-containing-grid metallization structure that contains a metal phosphorus layer as a diffusion barrier is provided. The copper-containing-grid metallization structure includes, from bottom to top, an electroplated metal phosphorus layer that does not include copper or a copper alloy located within a grid pattern formed on a front side surface of a semiconductor substrate, and an electroplated copper-containing layer. A method of forming such a structure is also provided.Type: GrantFiled: March 14, 2016Date of Patent: April 23, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kathryn C. Fisher, Qiang Huang, Satyavolu S. Papa Rao
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Patent number: 10167443Abstract: A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution removes an etch residue that includes a majority of hydrocarbons and at least one element selected from the group consisting of carbon, oxygen, fluorine, nitrogen and silicon. In one example, the aqueous solution may be cerium ammonium nitrate (Ce(NH4)(NO3)),(CAN).Type: GrantFiled: October 26, 2016Date of Patent: January 1, 2019Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ZEON CORPORATIONInventors: Robert L. Bruce, Sebastian U. Engelmann, Eric A. Joseph, Mahmoud Khojasteh, Masahiro Nakamura, Satyavolu S. Papa Rao, Bang N. To, George G. Totir, Yu Zhu
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Patent number: 10170644Abstract: A photovoltaic device is provided that includes a semiconductor substrate including a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion one lying on top of the other, wherein an upper exposed surface of the semiconductor substrate represents a front side surface of the semiconductor substrate. A plurality of patterned antireflective coatings is located on the front side surface to provide a grid pattern including a busbar region and finger regions. The busbar region includes at least a real line interposed between at least two dummy lines. A material stack including at least one metal layer located on the semiconductor substrate in the busbar region and the finger regions.Type: GrantFiled: March 27, 2017Date of Patent: January 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kathryn C. Fisher, Qiang Huang, Satyavolu S. Papa Rao, David L. Rath
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Patent number: 9786852Abstract: Embodiments of the invention include a method of fabrication of a semiconductor structure. The method of fabrication includes: Forming a trench in a first dielectric material down to a first conductive material of a bottom gate. A sidewall of the trench contacts a top surface of the first conductive material. Depositing a second conductive material on the sidewall of the trench, which forms an electrical connection with the first conductive material. Depositing a second dielectric material in the trench, and on the second conductive material. Depositing a gate dielectric material on the second conductive material and the dielectric materials. Forming a channel material on the gate dielectric material. Depositing another conductive material on the channel material and portions of the gate dielectric material to form a source terminal and a drain terminal.Type: GrantFiled: December 2, 2015Date of Patent: October 10, 2017Assignee: International Business Machines CorporationInventors: Aaron D. Franklin, Shu-Jen Han, Satyavolu S. Papa Rao, Joshua T. Smith
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Publication number: 20170200838Abstract: A photovoltaic device is provided that includes a semiconductor substrate including a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion one lying on top of the other, wherein an upper exposed surface of the semiconductor substrate represents a front side surface of the semiconductor substrate. A plurality of patterned antireflective coatings is located on the front side surface to provide a grid pattern including a busbar region and finger regions. The busbar region includes at least a real line interposed between at least two dummy lines. A material stack including at least one metal layer located on the semiconductor substrate in the busbar region and the finger regions.Type: ApplicationFiled: March 27, 2017Publication date: July 13, 2017Inventors: Kathryn C. Fisher, Qiang Huang, Satyavolu S. Papa Rao, David L. Rath
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Patent number: 9608134Abstract: A method of forming a photovoltaic device is provided that includes a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion, wherein an upper exposed surface of one of the semiconductor portions represents a front side surface of the semiconductor substrate. Patterned antireflective coating layers are formed on the front side surface of the semiconductor surface to provide a grid pattern including a busbar region and finger region. A mask having a shape that mimics each patterned antireflective coating layer is provided atop each patterned antireflective coating layer. A metal layer is electrodeposited on the busbar region and the finger regions. After removing the mask, an anneal is performed that reacts metal atoms from the metal layer react with semiconductor atoms from the busbar region and the finger regions forming a metal semiconductor alloy.Type: GrantFiled: January 29, 2015Date of Patent: March 28, 2017Assignee: International Business Machines CorporationInventors: Kathryn C. Fisher, Qiang Huang, Satyavolu S. Papa Rao, David L. Rath
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Publication number: 20170044470Abstract: A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution removes an etch residue that includes a majority of hydrocarbons and at least one element selected from the group consisting of carbon, oxygen, fluorine, nitrogen and silicon. In one example, the aqueous solution may be cerium ammonium nitrate (Ce(NH4)(NO3)),(CAN).Type: ApplicationFiled: October 26, 2016Publication date: February 16, 2017Inventors: Robert L. Bruce, Sebastian U. Engelmann, Eric A. Joseph, Mahmoud Khojasteh, Masahiro Nakamura, Satyavolu S. Papa Rao, Bang N. To, George G. Totir, Yu Zhu
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Patent number: 9536731Abstract: A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution removes an etch residue that includes a majority of hydrocarbons and at least one element selected from the group consisting of carbon, oxygen, fluorine, nitrogen and silicon. In one example, the aqueous solution may be cerium ammonium nitrate (Ce(NH4)(NO3)),(CAN).Type: GrantFiled: October 24, 2014Date of Patent: January 3, 2017Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ZEON CORPORATIONInventors: Robert L. Bruce, Sebastian U. Engelmann, Eric A. Joseph, Mahmoud Khojasteh, Masahiro Nakamura, Satyavolu S. Papa Rao, Bang N. To, George G. Totir, Yu Zhu
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Publication number: 20160197208Abstract: A photovoltaic device, such as a solar cell, including a copper-containing-grid metallization structure that contains a metal phosphorus layer as a diffusion barrier is provided. The copper-containing-grid metallization structure includes, from bottom to top, an electroplated metal phosphorus layer that does not include copper or a copper alloy located within a grid pattern formed on a front side surface of a semiconductor substrate, and an electroplated copper-containing layer. A method of forming such a structure is also provided.Type: ApplicationFiled: March 14, 2016Publication date: July 7, 2016Inventors: Kathryn C. Fisher, Qiang Huang, Satyavolu S. Papa Rao
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Publication number: 20160087232Abstract: Embodiments of the invention include a method of fabrication of a semiconductor structure. The method of fabrication includes: Forming a trench in a first dielectric material down to a first conductive material of a bottom gate. A sidewall of the trench contacts a top surface of the first conductive material. Depositing a second conductive material on the sidewall of the trench, which forms an electrical connection with the first conductive material. Depositing a second dielectric material a in the trench, and on the second conductive material. Depositing a gate dielectric material on the second conductive material and the dielectric materials. Forming a channel material on the gate dielectric material. Depositing another conductive material on the channel material and portions of the gate dielectric material to form a source terminal and a drain terminal.Type: ApplicationFiled: December 2, 2015Publication date: March 24, 2016Inventors: Aaron D. Franklin, Shu-Jen Han, Satyavolu S. Papa Rao, Joshua T. Smith
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Patent number: 9284656Abstract: A photovoltaic device, such as a solar cell, including a copper-containing-grid metallization structure that contains a metal phosphorus layer as a diffusion barrier is provided. The copper-containing-grid metallization structure includes, from bottom to top, an electroplated metal phosphorus layer that does not include copper or a copper alloy located within a grid pattern formed on a front side surface of a semiconductor substrate, and an electroplated copper-containing layer. A method of forming such a structure is also provided.Type: GrantFiled: June 6, 2011Date of Patent: March 15, 2016Assignee: International Business Machines CorporationInventors: Kathryn C. Fisher, Qiang Huang, Satyavolu S. Papa Rao
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Patent number: 9246024Abstract: A photovoltaic device is provided that includes a semiconductor substrate including a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion one on top of the other. A plurality of patterned antireflective coating layers is located on a p-type semiconductor surface of the semiconductor substrate, wherein at least one portion of the p-type semiconductor surface of the semiconductor substrate is exposed. Aluminum is located directly on the at least one portion of the p-type semiconductor surface of the semiconductor substrate that is exposed.Type: GrantFiled: July 14, 2011Date of Patent: January 26, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kathryn C. Fisher, Qiang Huang, Satyavolu S. Papa Rao, Ming-Ling Yeh
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Patent number: 9246112Abstract: Embodiments of the invention include a method of fabrication and a semiconductor structure. The method of fabrication includes depositing a first dielectric material on a substrate, and forming a bottom gate including filling a first opening in the first dielectric layer with a first conductive material. Next, depositing a second dielectric material, and forming a trench in the second dielectric material down to the first conductive material. Next, depositing a second conductive material on the sidewall of the trench forming an electrical connection between the first conductive material and the second conductive material, depositing a third dielectric material in the trench, and removing excess material not in the trench. Next, depositing a gate dielectric layer, and forming a channel layer of carbon nanotubes on the gate dielectric layer. Lastly, depositing a third conductive material on the channel layer forming source and drain terminals.Type: GrantFiled: January 8, 2014Date of Patent: January 26, 2016Assignee: International Business Machines CorporationInventors: Aaron D. Franklin, Shu-Jen Han, Satyavolu S. Papa Rao, Joshua T. Smith
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Patent number: 9188578Abstract: An anti-retraction capping material is formed on a surface of a nanowire that is located upon a dielectric membrane. A gap is then formed into the anti-retraction capping material and nanowire forming first and second capped nanowire structures of a nanodevice. The nanodevice can be used for recognition tunneling measurements including, for example DNA sequencing. The anti-retraction capping material serves as a mobility barrier to pin, i.e., confine, a nanowire portion of each of the first and second capped nanowire structures in place, allowing long-term structural stability. In some embodiments, interelectrode leakage through solution during recognition tunneling measurements can be minimized.Type: GrantFiled: September 30, 2013Date of Patent: November 17, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Yann A. N. Astier, Jingwei Bai, Satyavolu S. Papa Rao, Kathleen B. Reuter, Joshua T. Smith
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Patent number: 9182369Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nanogap.Type: GrantFiled: June 19, 2013Date of Patent: November 10, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Yann Astier, Jingwei Bai, Michael A. Guillorn, Satyavolu S. Papa Rao, Joshua T. Smith
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Patent number: 9128078Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nanogap.Type: GrantFiled: July 18, 2013Date of Patent: September 8, 2015Assignee: International Business Machines CorporationInventors: Yann Astier, Jingwei Bai, Michael A. Guillorn, Satyavolu S. Papa Rao, Joshua T. Smith
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Patent number: 9097698Abstract: An anti-retraction capping material is formed on a surface of a nanowire that is located upon a dielectric membrane. A gap is then formed into the anti-retraction capping material and nanowire forming first and second capped nanowire structures of a nanodevice. The nanodevice can be used for recognition tunneling measurements including, for example DNA sequencing. The anti-retraction capping material serves as a mobility barrier to pin, i.e., confine, a nanowire portion of each of the first and second capped nanowire structures in place, allowing long-term structural stability. In some embodiments, interelectrode leakage through solution during recognition tunneling measurements can be minimized.Type: GrantFiled: January 29, 2015Date of Patent: August 4, 2015Assignee: International Business Machines CorporationInventors: Yann A. N. Astier, Jingwei Bai, Satyavolu S. Papa Rao, Kathleen B. Reuter, Joshua T. Smith
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Publication number: 20150194619Abstract: Embodiments of the invention include a method of fabrication and a semiconductor structure. The method of fabrication includes depositing a first dielectric material on a substrate, and forming a bottom gate comprising filling a first opening in the first dielectric layer with a first conductive material. Next, depositing a second dielectric material, and forming a trench in the second dielectric material down to the first conductive material. Next, depositing a second conductive material on the sidewall of the trench forming an electrical connection between the first conductive material and the second conductive material, depositing a third dielectric material in the trench, and removing excess material not in the trench. Next, depositing a gate dielectric layer, and forming a channel layer of carbon nanotubes on the gate dielectric layer. Lastly, depositing a third conductive material on the channel layer forming source and drain terminals.Type: ApplicationFiled: January 8, 2014Publication date: July 9, 2015Applicant: International Business Machines CorporationInventors: Aaron D. Franklin, Shu-Jen Han, Satyavolu S. Papa Rao, Joshua T. Smith
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Publication number: 20150153320Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nano gap.Type: ApplicationFiled: January 28, 2015Publication date: June 4, 2015Inventors: Yann Astier, Jingwei Bai, Michael A. Guillorn, Satyavolu S. Papa Rao, Joshua T. Smith