Patents by Inventor Satyavolu Srinivas Papa Rao

Satyavolu Srinivas Papa Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8604587
    Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and includes surface protection cladding (109) for the copper metal (104b) of the top metal interconnect.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: December 10, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Edmund Burke, Satyavolu Srinivas Papa Rao, Timothy Alan Rost
  • Patent number: 8211794
    Abstract: In accordance with the invention, there are diffusion barriers, integrated circuits, and semiconductor devices and methods of fabricating them. The method of fabricating a diffusion barrier can include providing a dielectric layer, forming a first silicon enriched layer over the dielectric layer by exposing the dielectric layer to a silicon-containing ambient, and forming a barrier layer over the first silicon enriched layer.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: July 3, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Valli Arunachalam, Satyavolu Srinivas Papa Rao, Sanjeev Aggarwal, Stephan Grunow
  • Patent number: 7781884
    Abstract: The density of components in integrated circuits (ICs) is increasing with time. The density of heat generated by the components is similarly increasing. Maintaining the temperature of the components at reliable operating levels requires increased thermal transfer rates from the components to the IC package exterior. Dielectric materials used in interconnect regions have lower thermal conductivity than silicon dioxide. This invention comprises a heat pipe located in the interconnect region of an IC to transfer heat generated by components in the IC substrate to metal plugs located on the top surface of the IC, where the heat is easily conducted to the exterior of the IC package. Refinements such as a wicking liner or reticulated inner surface will increase the thermal transfer efficiency of the heat pipe. Strengthening elements in the interior of the heat pipe will provide robustness to mechanical stress during IC manufacture.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: August 24, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer Kumar Ajmera, Phillip D. Matz, Stephan Grunow, Satyavolu Srinivas Papa Rao
  • Patent number: 7678713
    Abstract: The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a hardness and a modulus of elasticity, and subjecting the dielectric layer to an energy beam, thereby causing the hardness or modulus of elasticity to increase in value.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: March 16, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Ting Y. Tsui, Andrew McKerrow, Satyavolu Srinivas Papa Rao, Robert Kraft
  • Patent number: 7674707
    Abstract: Devices and methods are presented to fabricate diffusion barrier layers on a substrate. Presently, barrier layers comprising a nitride layer and a pure metal layer are formed using a physical vapor deposition (PVD) process that requires multiple ignition steps, and results in nitride-layer thicknesses of no less than 2 nm. This invention discloses devices and process to produce nitride-layers of less than <1 nm, while allowing for formation of a pure metal layer on the nitride-layer without re-igniting the plasma. To achieve this, the flow of nitrogen gas is cut off either before the plasma is ignited, or before the formation of a continuous-flow plasma. This ensures that a limited number of nitrogen atoms is deposited in conjunction with metal atoms on the substrate, thereby allowing for controlled thickness of the nitride layer.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: March 9, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Noel M. Russell, Satyavolu Srinivas Papa Rao, Stephan Grunow
  • Patent number: 7642619
    Abstract: A semiconductor device, such as an inductor, is formed with an air gap. A first level has an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures. An inter-level dielectric layer is formed over the first level. An extraction via is formed through the intra-metal dielectric layer and inter-level dielectric layer. An air gap is formed between inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using a supercritical fluid process, and forming a non-conformal layer to seal the extraction via. The air gap may be filled with an inert gas, like argon or nitrogen.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: January 5, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Phillip D. Matz, Stephan Grunow, Satyavolu Srinivas Papa Rao
  • Publication number: 20090261453
    Abstract: A semiconductor device, such as an inductor, is formed with an air gap. A first level has an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures. An inter-level dielectric layer is formed over the first level. An extraction via is formed through the intra-metal dielectric layer and inter-level dielectric layer. An air gap is formed between inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using a supercritical fluid process, and forming a non-conformal layer to seal the extraction via. The air gap may be filled with an inert gas, like argon or nitrogen.
    Type: Application
    Filed: June 23, 2009
    Publication date: October 22, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Phillip D. Matz, Stephan Grunow, Satyavolu Srinivas Papa Rao
  • Patent number: 7566627
    Abstract: In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of making an inductor with an air gap can include fabricating a first level of inductor in an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures, forming an inter-level dielectric layer over the first level and repeating the steps to form two or more levels of inductor. The method can also include forming an extraction via, forming an air gap between the inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using super critical fluid process, and forming a non-conformal layer to seal the extraction via.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: July 28, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Phillip D Matz, Stephan Grunow, Satyavolu Srinivas Papa Rao
  • Publication number: 20090166865
    Abstract: Devices and methods are presented to fabricate diffusion barrier layers on a substrate. Presently, barrier layers comprising a nitride layer and a pure metal layer are formed using a physical vapor deposition (PVD) process that requires multiple ignition steps, and results in nitride-layer thicknesses of no less than 2 nm. This invention discloses devices and process to produce nitride-layers of less than <1 nm, while allowing for formation of a pure metal layer on the nitride-layer without re-igniting the plasma. To achieve this, the flow of nitrogen gas is cut off either before the plasma is ignited, or before the formation of a continuous-flow plasma. This ensures that a limited number of nitrogen atoms is deposited in conjunction with metal atoms on the substrate, thereby allowing for controlled thickness of the nitride layer.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventors: Noel M. RUSSELL, Satyavolu Srinivas Papa Rao, Stephan Grunow
  • Patent number: 7531398
    Abstract: A semiconductor device is fabricated having a metal stress inducing layer that facilitates channel mobility. A gate dielectric layer is formed over a semiconductor substrate. The metal stress inducing layer is formed over the gate dielectric layer. The metal stress inducing layer has a selected conductivity type and is formed and composed to yield a select stress amount and type. A gate layer, such as a polysilicon layer, is formed over the metal stress inducing layer. The gate layer and the metal stress inducing layer are patterned to define gate structures.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: May 12, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Zhibo Zhang, Cloves Rinn Cleavelin, Michael Francis Pas, Stephanie Watts Butler, Mike Watson Goodwin, Satyavolu Srinivas Papa Rao
  • Publication number: 20090087956
    Abstract: State of the art Integrated Circuits (ICs) encompass a variety of circuits, which have a wide variety of contact densities as measured in regions from 10 to 1000 microns in size. Fabrication processes for contacts have difficulty with high and low contact densities on the same IC, leading to a high incidence of electrical shorts and reduced operating speed of the circuits. This problem is expected to worsen as feature sizes shrink in future technology nodes. This invention is an electrically non-functional contact, known as a dummy contact, that is utilized to attain a more uniform distribution of contacts across an IC, which allows contact fabrication processes to produce ICs with fewer defects, and a method for forming said dummy contacts in ICs.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 2, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Satyavolu Srinivas Papa Rao, Mona M. Eissa, Christopher Lyle Borst, Noel M. Russell, Stanley Monroe Smith
  • Publication number: 20090085197
    Abstract: The density of components in integrated circuits (ICs) is increasing with time. The density of heat generated by the components is similarly increasing. Maintaining the temperature of the components at reliable operating levels requires increased thermal transfer rates from the components to the IC package exterior. Dielectric materials used in interconnect regions have lower thermal conductivity than silicon dioxide. This invention comprises a heat pipe located in the interconnect region of an IC to transfer heat generated by components in the IC substrate to metal plugs located on the top surface of the IC, where the heat is easily conducted to the exterior of the IC package. Refinements such as a wicking liner or reticulated inner surface will increase the thermal transfer efficiency of the heat pipe. Strengthening elements in the interior of the heat pipe will provide robustness to mechanical stress during IC manufacture.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Kumar Ajmera, Phillip D. Matz, Stephan Grunow, Satyavolu Srinivas Papa Rao
  • Publication number: 20090001510
    Abstract: In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of making an inductor with an air gap can include fabricating a first level of inductor in an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures, forming an inter-level dielectric layer over the first level and repeating the steps to form two or more levels of inductor. The method can also include forming an extraction via, forming an air gap between the inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using super critical fluid process, and forming a non-conformal layer to seal the extraction via.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventors: Phillip D Matz, Stephan Grunow, Satyavolu Srinivas Papa Rao
  • Publication number: 20080290515
    Abstract: In accordance with the invention, there are diffusion barriers, integrated circuits, and semiconductor devices and methods of fabricating them. The method of fabricating a diffusion barrier can include providing a dielectric layer, forming a first silicon enriched layer over the dielectric layer by exposing the dielectric layer to a silicon-containing ambient, and forming a barrier layer over the first silicon enriched layer.
    Type: Application
    Filed: May 25, 2007
    Publication date: November 27, 2008
    Inventors: Valli Arunachalam, Satyavolu Srinivas Papa Rao, Sanjeev Aggarwal, Stephen Grunow
  • Publication number: 20080153393
    Abstract: A method for serially polishing a plurality of semiconductor wafers, wherein a CMP apparatus having a first polishing pad and a second polishing pad is provided. A first slurry composition is disposed between the first polishing pad and a first wafer when the first wafer is in a first state, and a first polishing on the first wafer via the first polishing pad and first slurry composition is commenced at a first commencement time. A second slurry composition is disposed between the second polishing pad and a second wafer when the second wafer is in a second state, and a second polishing on the second wafer via the second polishing pad and second slurry is commenced at a second commencement time, wherein the second commencement time differs from the first commencement time by a first intermediate period. One or more of the first wafer and the second wafer is rinsed with a pre-rinse agent for at least a portion of the first intermediate period.
    Type: Application
    Filed: March 12, 2007
    Publication date: June 26, 2008
    Inventors: Linlin Chen, Li Chen, Satyavolu Srinivas Papa Rao
  • Publication number: 20080096338
    Abstract: A semiconductor device is fabricated having a metal stress inducing layer that facilitates channel mobility. A gate dielectric layer is formed over a semiconductor substrate. The metal stress inducing layer is formed over the gate dielectric layer. The metal stress inducing layer has a selected conductivity type and is formed and composed to yield a select stress amount and type. A gate layer, such as a polysilicon layer, is formed over the metal stress inducing layer. The gate layer and the metal stress inducing layer are patterned to define gate structures.
    Type: Application
    Filed: October 19, 2006
    Publication date: April 24, 2008
    Inventors: Zhibo Zhang, Cloves Rinn Cleavelin, Michael Francis Pas, Stephanie Watts Butler, Mike Watson Goodwin, Satyavolu Srinivas Papa Rao
  • Publication number: 20080076191
    Abstract: A ferroelectric capacitor stack is formed over a metal-dielectric interconnect layer. After forming the interconnect layer, the surface of the interconnect layer is treated with gas cluster ion beam (GCIB) processing. Prior to this processing, the surface typically includes metal recesses. The GCIB processing smoothes these recesses and provides a more level surface on which to form the ferroelectric capacitor stack. When the ferroelectric capacitor stack is formed on this leveled surface, leakage is reduced and yields increased as compared to the case where GCIB processing is not used.
    Type: Application
    Filed: September 22, 2006
    Publication date: March 27, 2008
    Inventors: Lindsey Hall, Sanjeev Aggarwal, Satyavolu Srinivas Papa Rao
  • Patent number: 7338893
    Abstract: A device employs damascene layers with a pore sealing liner and includes a semiconductor body. A metal interconnect layer comprising a metal interconnect is formed over the semiconductor body. A dielectric layer is formed over the metal interconnect layer. A conductive trench feature and a conductive via feature are formed in the dielectric layer. A pore sealing liner is formed only along sidewall of the conductive via feature and along sidewalls and bottom surfaces of the conductive trench feature. The pore sealing liner is not substantially present along a bottom surface of the conductive via feature.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: March 4, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Edward Raymond Engbrecht, Satyavolu Srinivas Papa Rao, Sameer Kumar Ajmera, Stephan Grunow
  • Patent number: 7212607
    Abstract: An x-ray confocal defect detection system comprises an x-ray source, a confocal component, and defect detectors and operates on a target portion of a semiconductor device. The x-ray source generates x-ray energy. The semiconductor device includes a plurality of formed layers. The target portion is a selected layer or portion of the plurality of formed layers. At least a portion of the x-ray is transmitted through the semiconductor device as transmitted x-ray. The confocal component receives the transmitted x-ray and passes target x-ray intensity from the target portion of the transmitted x-ray energy. Detectors receive the target x-ray from the confocal component from which defect analysis can be performed.
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: May 1, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Satyavolu Srinivas Papa Rao, Richard L. Guldi, Basab Chatterjee
  • Patent number: 7189615
    Abstract: The formation of a MIM (metal insulator metal) capacitor (164) and concurrent formation of a resistor (166) is disclosed. A copper diffusion barrier (124) is formed over a copper deposition (110) that serves as a bottom electrode (170) of the capacitor (164). The copper diffusion barrier (124) mitigates unwanted diffusion of copper from the copper deposition (110), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface (125) of the deposition of copper/bottom electrode. Subsequently, layers of dielectric (150) and conductive (152) materials are applied to form a dielectric (172) and top electrode (174) of the MIM capacitor (164), respectively, where the layer of conductive top electrode material (152) also functions to concurrently develop the resistor (166) on the same chip as the capacitor (164).
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: March 13, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Satyavolu Srinivas Papa Rao, Darius Lammont Crenshaw, Stephan Grunow, Kenneth D. Brennan, Somit Joshi, Montray Leavy, Phillip D. Matz, Sameer Kumar Ajmera, Yuri E. Solomentsev