Patents by Inventor Satyendra Chauhan

Satyendra Chauhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9563866
    Abstract: In a method for estimating a complexity of a computing job, selected data objects relevant to a data repository are retrieved. In addition, points are assigned to multiple elements of the selected data objects according to a predefined schedule and scores for the selected data objects are calculated by applying a mathematical function to the multiple elements and complexities of the data objects are estimated based upon the calculated scores and the predefined schedule. In addition, a complexity of the computing job is estimated based upon the estimated complexities of the data objects and the estimated complexity of the computing job is stored.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: February 7, 2017
    Assignee: ACCENTURE GLOBAL SERVICES LIMITED
    Inventors: Dharmesh Rajendra Mehta, Sudha Sahasrabudhe, Shagufta Shashank Kohli, Anu Tayal, Vineet Tiyagi, Shalini Agarwal, Santosh Ray, Satyendra Chauhan, Kalamalla Basha
  • Patent number: 7915080
    Abstract: A method for bonding IC die to TSV wafers includes bonding at least one singulated IC die to respective ones of a plurality of IC die on a TSV wafer that includes a top semiconductor surface and TSV precursors including embedded TSV tips to form a die-wafer stack. The die-wafer stack is thinned beginning from the bottom surface of the TSV wafer to form a thinned die-wafer stack. The thinning includes exposing the embedded TSV tips to provide electrical access thereto from the bottom surface of the TSV wafer. The thinned die-wafer stack can be singulated to form a plurality of thinned die stacks.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: March 29, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Yoshimi Takahashi, Masood Murtuza, Rajiv Dunne, Satyendra Chauhan
  • Publication number: 20100257116
    Abstract: In a method for estimating a complexity of a computing job, selected data objects relevant to a data repository are retrieved. In addition, points are assigned to multiple elements of the selected data objects according to a predefined schedule and scores for the selected data objects are calculated by applying a mathematical function to the multiple elements and complexities of the data objects are estimated based upon the calculated scores and the predefined schedule. In addition, a complexity of the computing job is estimated based upon the estimated complexities of the data objects and the estimated complexity of the computing job is stored.
    Type: Application
    Filed: April 5, 2010
    Publication date: October 7, 2010
    Applicant: Accenture Global Services, GmbH
    Inventors: Dharmesh Rajendra Mehta, Sudha Sahasrabudhe, Shagufta Shashank Kohli, Anu Tayal, Vineet Tiyagi, Shalini Agarwal, Santosh Ray, Satyendra Chauhan, Kalamalla Basha
  • Publication number: 20100159643
    Abstract: A method for bonding IC die to TSV wafers includes bonding at least one singulated IC die to respective ones of a plurality of IC die on a TSV wafer that includes a top semiconductor surface and TSV precursors including embedded TSV tips to form a die-wafer stack. The die-wafer stack is thinned beginning from the bottom surface of the TSV wafer to form a thinned die-wafer stack. The thinning includes exposing the embedded TSV tips to provide electrical access thereto from the bottom surface of the TSV wafer. The thinned die-wafer stack can be singulated to form a plurality of thinned die stacks.
    Type: Application
    Filed: October 8, 2009
    Publication date: June 24, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: YOSHIMI TAKAHASHI, MASOOD MURTUZA, RAJIV DUNNE, SATYENDRA CHAUHAN
  • Publication number: 20060180919
    Abstract: A package, comprising a substrate having a surface comprising metal traces, a solder mask covering at least a portion of the surface of the substrate, and a first aperture through the solder mask exposing a plurality of metal traces.
    Type: Application
    Filed: April 17, 2006
    Publication date: August 17, 2006
    Inventors: Satyendra Chauhan, Masood Murtuza
  • Publication number: 20060033210
    Abstract: A package is disclosed, which includes a substrate, a solder masker, and a first aperture through the solder mask. The substrate has a surface on which metal traces are formed. The solder mask covers at least a portion of the surface of the substrate. And the first aperture through the solder mask exposes a plurality of the metal traces.
    Type: Application
    Filed: August 12, 2004
    Publication date: February 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Satyendra Chauhan, Masood Murtuza