Patents by Inventor Satyendra S. Sethi

Satyendra S. Sethi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6642529
    Abstract: A method for inspecting features on a reticle is provided. The method includes providing a layout design of a test feature and transferring the layout design of the test feature onto the reticle. After the test feature is transferred onto the reticle, an image of the transferred layout design is captured to determine whether or not the transfer is acceptable. This determination is made by comparing the captured image of the transferred layout design against the layout design of the test feature. The comparison ascertains deviations between the captured image and the layout design and determines if the deviations fall within a user specified range.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: November 4, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Sudhir G. Subramanya, Clifford Takemoto, Satyendra S. Sethi
  • Patent number: 6433854
    Abstract: In one example embodiment, a method of forming a pattern in a photoresist material includes illuminating a portion of the photoresist material according to the pattern and positioning a filter in a path of the light. The filter includes a number of regions upon which a filtering material has been. The filtering material has a variable characteristic that is independently adjustable for each region to enhance the uniformity of the intensity of the light. Such characteristics include the thickness of the filtering material, the size of the portion of the region that is covered by the filtering material, or a voltage, current, electric field, or magnetic field applied to the filtering material of each region.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: August 13, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Daniel C. Baker, Kouros Ghandehari, Satyendra S. Sethi
  • Patent number: 6313542
    Abstract: The present invention is directed to a method and apparatus for detecting edges through one or more opaque, planarized layers of material. Exemplary embodiments can take full advantage of decreased size geometries associated, such as 0.25 micron technologies, without suffering inaccuracies due to wafer misalignment during processing (e.g., during a photolithographic process). The invention is applicable to any process where an edge is to be detected through a planarized layer which is opaque to visible light. In an exemplary embodiment, an edge of an alignment mark can be detected using an energy source having a wavelength and angle of incidence specifically selected with respect to the optical characteristics and thickness of particular material layers being processed.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: November 6, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Dipankar Pramanik, Kouros Ghandehari, Satyendra S. Sethi, Daniel C. Baker
  • Publication number: 20010026360
    Abstract: In one example embodiment, a method of forming a pattern in a photoresist material includes illuminating a portion of the photoresist material according to the pattern and positioning a filter in a path of the light. The filter includes a number of regions upon which a filtering material has been. The filtering material has a variable characteristic that is independently adjustable for each region to enhance the uniformity of the intensity of the light. Such characteristics include the thickness of the filtering material, the size of the portion of the region that is covered by the filtering material, or a voltage, current, electric field, or magnetic field applied to the filtering material of each region.
    Type: Application
    Filed: June 5, 2001
    Publication date: October 4, 2001
    Applicant: Philips Semiconductors, Inc.
    Inventors: Daniel C. Baker, Kouros Ghandehari, Satyendra S. Sethi
  • Patent number: 6262795
    Abstract: An apparatus for forming a pattern in a photoresist material includes a light source to provide light for illuminating a portion of the photoresist material according to the pattern and a filter positioned in a path of the light. The filter includes a number of regions upon which a filtering material has been. The filtering material has a variable characteristic that is independently adjustable for each region to enhance the uniformity of the intensity of the light. Such characteristics include the thickness of the filtering material, the size of the portion of the region that is covered by the filtering material, or a voltage, current, electric field, or magnetic field applied to the filtering material of each region.
    Type: Grant
    Filed: August 28, 1998
    Date of Patent: July 17, 2001
    Assignee: Philip Semiconductors, Inc.
    Inventors: Daniel C. Baker, Kouros Ghandehari, Satyendra S. Sethi
  • Patent number: 5952135
    Abstract: A method and apparatus for the alignment of a semiconductor device in preparation for patterning a layer of the device includes using an alignment apparatus which has one or more light sources for producing light at two or more alignment wavelengths. Typically, the semiconductor device will include alignment structures that are to be aligned with corresponding alignment markers on a photomask which contains the desired pattern. The alignment structures on the semiconductor device are often depressions or trenches in a layer of the device. The alignment apparatus determines the position of the alignment structures by observing the contrast in the intensity of light reflected off the region of the device containing the alignment structure and the region of the device adjacent to the alignment structure. This contrast in the intensity of light is wavelength dependent.
    Type: Grant
    Filed: November 19, 1997
    Date of Patent: September 14, 1999
    Assignee: VLSI Technology
    Inventors: Kouros Ghandehari, Satyendra S. Sethi, Daniel C. Baker
  • Patent number: 5852497
    Abstract: The present invention is directed to a method and apparatus for detecting edges through one or more opaque, planarized layers of material. Exemplary embodiments can take full advantage of decreased size geometries associated, such as 0.25 micron technologies, without suffering inaccuracies due to wafer misalignment during processing (e.g., during a photolithographic process). The invention is applicable to any process where an edge is to be detected through a planarized layer which is opaque to visible light. In an exemplary embodiment, an edge of an alignment mark can be detected using an energy source having a wavelength and angle of incidence specifically selected with respect to the optical characteristics and thickness of particular material layers being processed.
    Type: Grant
    Filed: August 28, 1997
    Date of Patent: December 22, 1998
    Assignee: VLSI Technology, Inc.
    Inventors: Dipankar Pramanik, Kouros Ghandehari, Satyendra S. Sethi, Daniel C. Baker
  • Patent number: 5443941
    Abstract: An antireflective coating used in the photolithography process is applied and removed in a plasma reactor. The halocarbon plasma polymer such as fluorocarbon plasma polymer of the present invention provides an improved antireflective coating.
    Type: Grant
    Filed: March 1, 1993
    Date of Patent: August 22, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Anand J. Bariya, Satyendra S. Sethi, Kevin C. Brown