Abstract: Write operations that simultaneously program multiple memory cells on the same word line in an MBPC Flash memory employ word line voltage variation, programming pulse width variation, and data-dependent bit line and/or source line biasing to achieve uniform programming accuracy across a range of target threshold voltages. A first type of write operation reaches different target threshold voltages during different time intervals, but uses word line signals that optimize threshold voltage resolution regardless of the target threshold voltage. A second type uses bit line and/or source line biases that depend on the multi-bit data values being written so that different memory cells reach different target threshold voltage at about the same time. Source line biasing can also reduce bit line leakage current through unselected memory cells during read or verify operations. A memory includes divided source lines that permit separate data-dependent source biasing.

Abstract: A memory transistor having a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. An erase operation can use a negative voltage on the control and a positive voltage on an underlying well or source/drain region to cause tunneling that discharges one or both floating gates. Applying a limited current to a source/drain region during an erase operation can cause the source/drain region and a floating gate to rise together and avoid band-to-band tunneling and resulting hole injection into the floating gate.

Abstract: A contactless memory architecture has a column of bidirectional multi-bit memory cells between each adjacent pair of diffused lines in a bank. The architecture includes about half as many metal lines as diffused lines, and bank select cells at both ends of the bank. Most bank select cells connect respective metal lines to respective pairs of diffused lines. For a memory access, metal lines on one side of a selected bidirectional memory cell are biased to a first voltage, and metal lines on the other side of the selected bidirectional memory cell are biased to a second voltage. The first voltage is made higher than the second voltage to select one of the storage locations in the selected cell, and the second voltage is made higher than the first voltage to select the other of the storage locations in the selected cell.

Abstract: A memory transistor having a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. An erase operation can use a negative voltage on the control and a positive voltage on an underlying well or source/drain region to cause tunneling that discharges one or both floating gates. Applying a limited current to a source/drain region during an erase operation can cause the source/drain region and a floating gate to rise together and avoid band-to-band tunneling and resulting hole injection into the floating gate.

Abstract: A memory transistor having a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. An erase operation can use a negative voltage on the control and a positive voltage on an underlying well or source/drain region to cause tunneling that discharges one or both floating gates. Applying a limited current to a source/drain region during an erase operation can cause the source/drain region and a floating gate to rise together and avoid band-to-band tunneling and resulting hole injection into the floating gate.

Abstract: Write operations that simultaneously program multiple memory cells on the same word line in an MBPC or MLC non-volatile memory employ word line voltage variation, programming pulse width variation, and column line voltage variation to achieve uniform programming accuracy across a range of target threshold voltages. One type of write operation reaches target threshold voltages during respective time intervals and in each time interval uses programming parameters that optimize threshold voltage resolution for the target threshold voltage corresponding to that interval. During or at the end of write operations or the ends of each interval, remedial programming sequences can adjust the threshold voltages of memory cells that program slowly.

Abstract: Auto-tracking bit line reference schemes have common reference and normal word lines and generate a “½ cell current” reference by providing reference bit lines with pull-up devices having a different effective size from the pull-up devices for bit line or by programming reference cells to different levels. To provide a true “current mirror” connection of the pull-up devices of bit line and one or more reference bit lines, an additional bias bit line causes currents through the pull-up devices for the selected bit line and the reference bit lines to mirror current through the pull-up device for the bias bit line. Embodiments of the invention can be used with binary and multiple-bit-per cell memory and with a variety of sense amplifiers, memory array architectures, and memory cell structures.

Abstract: A Flash memory that stores data, code, and parameters and performs parallel operations employs uniform-size blocks in array planes. A redundancy system for the Flash memory uses a CAM and a RAM for address comparison and substitution when replacing addresses corresponding to defective memory elements. The uniform block size allows block replacement where spare blocks in the array planes replace defective blocks. To reduce access delays from signal propagation through the CAM and RAM, part of the input address such as the row address goes directly to decoders while another part of the input address such as the block address goes to the CAM array for comparison.

Abstract: A multi-bit-per-cell non-volatile memory performs periodic refresh operations. The refresh operations can be timed according to a maximum tolerable drift for threshold voltages representing the data and an expected rate of drift of the threshold voltage. The refresh operation can move data to different physical storage locations and extend the life of a non-volatile memory by avoiding repetitive erasing and writing of the same data value in the same memory cell. A memory mapping circuit in the memory adjusts for different storage configuration that the refresh operations create. In a particular embodiment, a refresh operation swaps the physical locations of two data blocks, and alternates between two mappings of physical addresses to logical addresses.

Abstract: A contactless memory architecture has a column of bidirectional multi-bit memory cells between each adjacent pair of diffused lines in a bank. The architecture includes about half as many metal lines as diffused lines, and bank select cells at both ends of the bank. Most bank select cells connect respective metal lines to respective pairs of diffused lines. For a memory access, metal lines on one side of a selected bidirectional memory cell are biased to a first voltage, and metal lines on the other side of the selected bidirectional memory cell are biased to a second voltage. The first voltage is made higher than the second voltage to select one of the storage locations in the selected cell, and the second voltage is made higher than the first voltage to select the other of the storage locations in the selected cell.

Abstract: Write operations that simultaneously program multiple memory cells on the same word line in an MBPC Flash memory employ word line voltage variation, programming pulse width variation, and data-dependent bit line and/or source line biasing to achieve uniform programming accuracy across a range of target threshold voltages. A first type of write operation reaches different target threshold voltages during different time intervals, but uses word line signals that optimize threshold voltage resolution regardless of the target threshold voltage. A second type uses bit line and/or source line biases that depend on the multi-bit data values being written so that different memory cells reach different target threshold voltage at about the same time. Source line biasing can also reduce bit line leakage current through unselected memory cells during read or verify operations. A memory includes divided source lines that permit separate data-dependent source biasing.

Abstract: In a nonvolatile floating-gate semiconductor memory device, a word line voltage supply circuit is configured to be able to apply gate voltages to the same memory cells such that the gate voltage applied at and after the second time is different from the gate voltage applied at the first time. At least one of the word line voltage supply circuit and the bit line voltage supply circuit is set to be able to apply a voltage to the same memory cells for a longer application period at the first time than at and after the second time. With this configuration, the threshold voltage distribution of the memory cells is controlled to be narrow.

Abstract: A memory transistor having a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. An erase operation can use a negative voltage on the control and a positive voltage on an underlying well or source/drain region to cause tunneling that discharges one or both floating gates. Applying a limited current to a source/drain region during an erase operation can cause the source/drain region and a floating gate to rise together and avoid band-to-band tunneling and resulting hole injection into the floating gate.

Abstract: Auto-tracking bit line reference schemes generate a “½ cell current” reference by programming reference cells to threshold voltages that are between threshold voltage levels used to represent data. A common word line can control both a selected memory cell and a reference cell to provide a reference current, and differential sense amplifiers can compare a bit line current to reference currents to thereby distinguish data values. Current through other reference cells can be mirrored to pull-up devices to further improve the tracking of the reference line and bit line currents. Embodiments of the invention can be used with binary and multiple-bit-per-cell memories and with a variety of memory array architectures and memory cell structures.

Abstract: Write operations that simultaneously program multiple memory cells on the same word line in an MBPC Flash memory employ word line voltage variation, programming pulse width variation, and data-dependent bit line and/or source line biasing to achieve uniform programming accuracy across a range of target threshold voltages. A first type of write operations reaches different target threshold voltages during different time intervals, but uses word line signals that optimize threshold voltage resolution regardless of the target threshold voltage. A second type uses bit line and/or source line biases that depend on the multi-bit data values being written so that different memory cells reach different target threshold voltage at about the same time. Source line biasing can also reduce bit line leakage current through unselected memory cells during read or verify operations. A memory includes divided source lines that permit separate data-dependent source biasing.

Abstract: A multi-bit-per-cell non-volatile memory performs refresh operations that move data to different physical storage locations. The movement of data may extend the life of a non-volatile memory by avoiding repetitive erasing and writing of the same data value in the same memory cell. A memory mapping circuit in the memory adjusts for different storage configuration that the refresh operations create. In a particular embodiment, a refresh operation swaps the physical locations of two data blocks, and alternates between two mappings of physical addresses to logical addresses.

Abstract: A memory transistor has a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel. The memory transistor effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. The direction of the channel current controls which floating gate receives channel hot electron injection during programming and which floating gate state is sensed during reading. A read operation biases the word line higher that the threshold voltage used to store data and compares the resulting channel to reference currents to identify a stored binary, analog, or multi-bit value. The threshold voltage range can include negative threshold voltages, which increases the available range for multi-bit-per-floating gate storage.

Abstract: A multi-bit-per-cell non-volatile memory performs refresh operations that move data to different physical storage locations. The movement of data may extend the life of a non-volatile memory by avoiding repetitive erasing and writing of the same data value in the same memory cell. A memory mapping circuit in the memory adjusts for different storage configuration that the refresh operations create. In a particular embodiment, a refresh operation swaps the physical locations of two data blocks, and alternates between two mappings of physical addresses to logical addresses.

Abstract: A memory transistor has a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel. The memory transistor effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. The direction of the channel current controls which floating gate receives channel hot electron injection during programming and which floating gate state is sensed during reading. A read operation biases the word line higher that the threshold voltage used to store data and compares the resulting channel to reference currents to identify a stored binary, analog, or multi-bit value. The threshold voltage range can include negative threshold voltages, which increases the available range for multi-bit-per-floating gate storage.

Abstract: A compact contactless Flash memory architecture has memory cells instead of isolation regions between adjacent diffused lines in rows of a bank and thereby increases the density of memory cells in the bank when compared to prior architectures. Diffused lines in the bank can be used as virtual ground lines or as bit lines depending on which column of the bank is selected for access. The architecture includes about half as many metal lines as diffused lines, and most bank select cells operate to connect respective metal lines to respective pairs of diffused lines.