Abstract: The noise reduction convolutional auto-encoding method includes the following tasks. A distorted image is received and input into a noise reduction convolutional auto-encoding model. In the noise reduction convolutional auto-encoding model, an image feature of the distorted image is transferred to a first deconvolution layer through skip-connection. A plurality of multi-stride encoding convolutional layers are performed for the distortion image to reduce a dimension. A same-dimensional encoding convolutional layer is then performed. According to the corresponding multi-stride encoding convolutional layers and same-dimensional encoding convolutional layers, the corresponding a plurality of decoding multi-stride convolutional layers and a same-dimensional decoding convolutional layers are upgraded. The result of up-scaled dimension is input into the same-dimensional decoding convolutional layer of a balanced channel using the first deconvolution layer.

Abstract: A method for generating a codebook based on a discrete cosine transform, suitable for an electronic device with a plurality of antennas is provided, including: generating an identity matrix, and the size of the identity matrix is related to the number of antennas of the electronic device; inputting a plurality of column vectors of the identity matrix into a discrete cosine transform formula to calculate a plurality of codeword elements corresponding to the column vectors; generating a plurality of codewords corresponding to the column vectors, the codewords corresponding to the column vectors comprise the codeword elements corresponding to the column vectors; multiplying the codewords by a coefficient related to the number of antennas; determining whether the calculation of all the codewords has been completed; and completing the codebook.

Abstract: The noise reduction convolutional auto-encoding method includes the following tasks. A distorted image is received and input into a noise reduction convolutional auto-encoding model. In the noise reduction convolutional auto-encoding model, an image feature of the distorted image is transferred to a first deconvolution layer through skip-connection. A plurality of multi-stride encoding convolutional layers are performed for the distortion image to reduce a dimension. A same-dimensional encoding convolutional layer is then performed. According to the corresponding multi-stride encoding convolutional layers and same-dimensional encoding convolutional layers, the corresponding plurality of decoding multi-stride convolutional layers and same-dimensional decoding convolutional layers are upscaled to obtain a reconstructed image. The result of the up-scaled dimension is input into the same-dimensional decoding convolutional layer of a balanced channel using the first deconvolution layer.

Abstract: The noise reduction convolutional auto-encoding method includes the following tasks. A distorted image is received and input into a noise reduction convolutional auto-encoding model. In the noise reduction convolutional auto-encoding model, an image feature of the distorted image is transferred to a first deconvolution layer through skip-connection. A plurality of multi-stride encoding convolutional layers are performed for the distortion image to reduce a dimension. A same-dimensional encoding convolutional layer is then performed. According to the corresponding multi-stride encoding convolutional layers and same-dimensional encoding convolutional layers, the corresponding a plurality of decoding multi-stride convolutional layers and a same-dimensional decoding convolutional layers are upgraded. The result of up-scaled dimension is input into the same-dimensional decoding convolutional layer of a balanced channel using the first deconvolution layer.

Abstract: A folded butterfly module performs a radix-22 butterfly operation, and includes: a buffer operable to store first and second to-be-stored data and output first and second stored data; a first multiplexer operable to output one of the second stored data and input data as first selection data; a butterfly operator performing a radix-2 butterfly operation on the first stored data and the first selection data to generate operation data and the second to-be-stored data; a second multiplexer operable to output one of the input data and the operation data as the first to-be-stored data; a third multiplexer operable to output one of the operation data and the second stored data as second selection data; and a multiplier generating output data that equal a product of the second selection data and twiddle data.

Abstract: A folded butterfly module performs a radix-22 butterfly operation, and includes: a buffer operable to store first and second to-be-stored data and output first and second stored data; a first multiplexer operable to output one of the second stored data and input data as first selection data; a butterfly operator performing a radix-2 butterfly operation on the first stored data and the first selection data to generate operation data and the second to-be-stored data; a second multiplexer operable to output one of the input data and the operation data as the first to-be-stored data; a third multiplexer operable to output one of the operation data and the second stored data as second selection data; and a multiplier generating output data that equal a product of the second selection data and twiddle data.

Abstract: A symbol time synchronization method for OFDM systems is disclosed. The invention presents a joint maximum-likelihood (ML) synchronization method for symbol time offset (STO) in OFDM systems. The method is developed in frequency domain under time-variant multipath channels. By analyzing the received frequency-domain data, a mathematical model for the joint effects of symbol time offset (STO), carrier frequency offset (CFO) and sampling clock frequency offset (SCFO) is derived. The results are used to formulate a log-likelihood function of two consecutive symbols. The joint estimation's method is robust, because it exhibits high performances in high mobility and time-variant multipath fading channels.

Abstract: A cyclic comparison method for an LDPC decoder. The nth element of the input k elements, wherein n=1, . . . , k, is sequentially removed by the corresponding comparator to obtain k first level sequences. Next, pairs of two elements selected from the k elements are used to form k second level sequences. The preceding step is repeated k×?log2(k?1)? times to obtain k output results. Either of one first level sequences and one output results contains (k?1) elements. The first level sequences are compared with the output results to determine whether they are identical. If they are identical, the process stops. If they are not identical, the abovementioned step is repeated to obtain new output results. The cyclic comparison method of the present invention needs only k×?log2(k?1)? comparisons to obtain output results. Thus, the present invention can reduce the number of basic operations and can apply to any input number.

Abstract: The present invention discloses a set-cyclic comparison method for an LDPC (Low-Density Parity-Check) decoder, which applies to a CNU (Check Node Unit) or a VNU (Variable Node Unit). In the systematized method of the present invention, all the input elements are initialized to obtain a matrix. Based on the symmetry of the matrix and the similarity between the rows of the matrix are sequentially formed different sets respectively corresponding to the horizontally-continuous elements having the maximum iteration number in the horizontal and vertical directions, the symmetric non-continuous non-boundary elements, and the boundary elements plus the end-around neighboring elements in the same row. The present invention applies to any input number. Via the large intersection between the compared sets, the present invention can effectively reduce the number of comparison calculations and greatly promote the performance of an LDPC decoder.

Abstract: A fast division method which uses a smaller quotient digit set of {?1, 1} than {?1, 0, 1} that is used by known algorithms, therefore accelerates the speed of calculation. Partial remainders can be computed with the signals of remainders decided independently and in parallel. By taking the absolute values of the remainders, we can successively subtract the remainders without the need of knowing the signs of remainders, while signs of the remainders can be decided in parallel and independently at the same time. The algorithm adopts non-restoring division operation and CSA type of operation for fast subtraction. The algorithm is also an on-line algorithm that facilitates highly pipelined operation while it is much simpler than the existing on-line algorithms.

Abstract: A symbol time synchronization method for OFDM systems is disclosed. The invention presents a joint maximum-likelihood (ML) synchronization method for symbol time offset (STO) for OFDM systems. The method is developed in frequency-domain under time-variant multipath channels. By analyzing the received frequency-domain data, a mathematical model for the joint effects of symbol time offset (STO), carrier frequency offset (CFO) and sampling clock frequency offset (SCFO) is derived. The results are used to formulate a log-likelihood function of two consecutive symbols. The joint estimation's method is robust, because it exhibits high performances in high mobility and time-variant multipath fading channels.

Abstract: The present invention discloses a set-cyclic comparison method for an LDPC (Low-Density Parity-Check) decoder, which applies to a CNU (Check Node Unit) or a VNU (Variable Node Unit). In the systematized method of the present invention, all the input elements are initialized to obtain a matrix. Based on the symmetry of the matrix and the similarity between the rows of the matrix are sequentially formed different sets respectively corresponding to the horizontally-continuous elements having the maximum iteration number in the horizontal and vertical directions, the symmetric non-continuous non-boundary elements, and the boundary elements plus the end-around neighboring elements in the same row. The present invention applies to any input number. Via the large intersection between the compared sets, the present invention can effectively reduce the number of comparison calculations and greatly promote the performance of an LDPC decoder.

Abstract: The present invention discloses a cyclic comparison method for an LDPC decoder, which applies to the comparators used in an LDPC decoder. According to the cyclic comparison algorithm of the present invention, the nth element of the input k elements, wherein n=1, . . . , k, is sequentially removed by the corresponding comparator to obtain k first series. Next, pairs of two elements selected from the k elements are used to form k second series. The preceding step is repeated k×log2(k?1) times to obtain k completion series. Either of one first series and one completion series contains (k?1) elements. The first series are compared with the completion series to determine whether they are identical. If they are identical, the process stops. If they are not identical, the abovementioned step is repeated to obtain new completion series. The cyclic comparison method of the present invention needs only k×log2(k?1) comparisons to obtain completion series.

Abstract: A blind equalizer structure is devised which employs an efficient filter structure for the convolution operation therein. Associated with this filter structure, two equalizer coefficient estimation (i.e., coefficient adaptation) techniques are also devised, one of which is the basic technique and the other is a reduced-complexity version of the basic technique referred to as the sign technique. The efficient filter structure reduces the amount of multiplications needed for convolution by about a half at the expense of about the same amount of increase in needed additions. Because in digital circuit implementation, multiplications are much more complicated than additions, especially when such operations are carried out on complex entities, the proposed equalizer structure can reduce the complexity of the convolution operation therein by approximately a half, thereby reducing significantly the complexity of the complete equalizer and consequently the complexity of the receiver in a digital transmission system.

Abstract: A method is disclosed of modification of parameters of audio signals by dividing a digital signal converted from an original analog signal into sound frames, modifying a pitch and a playing rate of the digital signal within a frame and subsequent successive splicing a last modified frame with a first non-modified frame and calculating the mean absolute error to define the best splicing point in terms of producing minimal or no audible noise such that various sections of sound signals can be spliced together to achieve pitch and playing rate modification.An apparatus is also disclosed for implementing the method, the apparatus comprising input and output amplifiers, a low pass filter at the input and a low pass filter at the output, analog-to-digital and digital-to-analog converters, and a pitch shifting processor.

Abstract: An efficient micro architecture for motion estimation is proposed. It achieves better time and area performance over the existing structures. Through pipelining and effective manipulation of 2's complement arithmetic, the adder complexity is kept to its lowest, while speed for a combined subtraction, absolution and accumulation operations is made as fast as a carry-save addition (CSA).

Abstract: A fast square root method which separates the sign detection operation of the remainder from the remainder subtraction operation. By taking the absolute values of the remainders, the method can successively subtract the remainder without knowing the signs of remainders, while signs of the remainder can be detected in parallel fashion and independently. The method also uses a smaller square root digit set of {-1, 1} than {-1, 0, 1} that is used by many known fast algorithms. This digit set facilitates fast conversion of the results to binary representations. Together with some hardware design techniques, the square root method can be realized and pipelined in simple circuits.

Abstract: A fast divider is disclosed in the present invention. It utilizes a division method which uses a smaller quotient digit set of {-1, 1} than {-1, 0, 1} that used by known algorithms, therefore accelerates the speed of calculation. Partial remainders are computed with the signs of remainders decided independently and in parallel. By taking the absolute values of the remainders, the remainders are successively subtracted without the need of knowing the signs of remainders, while signs of the remainders can be decided in parallel and independently at the same time. The method adopts non-restoring division operation and CSA (carry save adder) type of operation for fast subtraction. The method is also an on-line algorithm that facilitates highly pipelined operations while it is much simpler than the existing on-line algorithms.