Patents by Inventor Sau Yan Keith Li
Sau Yan Keith Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11922533Abstract: A weighted average execution time associated with each execution stage of a plurality of execution stages used to process a plurality of frames in parallel is obtained. The processing of each of the plurality of frames is performed at each of the plurality of execution stages in a sequential order, starting with an initial execution stage and continuing with each subsequent execution stage. A first largest weighted average execution time associated with one of the plurality of execution stages is determined. A delay to the initial execution stage prior to processing a first next frame is applied. The delay is determined based on the first largest weighted average execution time.Type: GrantFiled: September 21, 2021Date of Patent: March 5, 2024Assignee: Nvidia CorporationInventors: Sau Yan Keith Li, Seth Schneider, Cody Robson, Lars Nordskog, Charles Hansen, Rouslan Dimitrov
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Patent number: 11886262Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.Type: GrantFiled: May 3, 2021Date of Patent: January 30, 2024Assignee: NVIDIA CorporationInventors: Sau Yan Keith Li, Thomas E. Dewey, Arthur Chen, Simon Lai, Amit Pabalkar, Santosh Nayak
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Publication number: 20230328302Abstract: A performance metrics of a receiver is obtained using frames of an application hosted by a server that are received via a network. The one or more performance metrics include information indicative of a current occupancy of a frame buffer corresponding to the receiver and information indicative of a target occupancy of the frame buffer corresponding to the receiver. The frame buffer of the receiver is used to queue frames of the application for display. A frame rate associated with rendering at least one next frame of the application is adjusted using the one or more performance metrics of the receiver to control population of the frame buffer. Subsequent frames of the application hosted by the server are rendered using the adjusted frame rate. Upon rendering the subsequent frames, the server sends the subsequent frames to the receiver for display.Type: ApplicationFiled: June 5, 2023Publication date: October 12, 2023Inventors: Rouslan Dimitrov, Viktor Grigoryevich Vandanov, Sau Yan Keith Li, James Howard, Scott Phillip Cutler
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Patent number: 11784906Abstract: A display device for measuring the end-to-end latency of a computing system. The computing system includes an input device, a computing device, and the display device. The display device is directly connected with the input device and receives input data packets generated by the input device in response to received user input events. The display device passes the input packets to the computing device for graphics processing. The display device measures the end-to-end latency comprising the sum of three latencies. A first latency comprises an input delay of the input device. A second latency comprises an amount of time between generation of the input packet and a corresponding change in pixel values caused by the input event at the display device. A third latency comprises a display latency. The display device also displays latency information associated with the measured end-to-end latency.Type: GrantFiled: June 4, 2020Date of Patent: October 10, 2023Assignee: NVIDIA CorporationInventors: Joohwan Kim, Benjamin Boudaoud, Josef B. Spjut, Morgan S. McGuire, Seth P. Schneider, Rouslan L. Dimitrov, Lars Nordskog, Cody J. Robson, Sau Yan Keith Li, Gerrit Ary Slavenburg, Tom J. Verbeure
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Publication number: 20230267063Abstract: In various examples, to real-time latency measurements in cloud gaming systems and applications are described. For instance, systems and methods may determine a latency associated with an application, such as a gaming application. The latency may include a computing device latency (e.g., a personal computer latency, a game console latency, a cloud-system latency, etc.), a peripheral device latency, a display latency, and/or an end-to-end latency (e.g., a system latency) that is based on the computing device latency, the peripheral device latency, and the display device. In some examples, the systems and methods are able to determine an entirety of the computing device latency, such as the input sampling latency, the application latency, the rendering latency, and the composition latency. In some examples, the systems and methods determine the latencies without the use of specialized hardware and/or without requiring physical input from a user.Type: ApplicationFiled: January 13, 2023Publication date: August 24, 2023Inventors: Sau Yan Keith Li, Prashant Khodade, Paul Alexander Hodgson, Seth Schneider, Prakshep Mehta, Sayantan Hensh
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Patent number: 11700402Abstract: A performance metrics of a receiver is obtained using frames of an application hosted by a server that are received via a network. The one or more performance metrics include information indicative of a current occupancy of a frame buffer corresponding to the receiver and information indicative of a target occupancy of the frame buffer corresponding to the receiver. The frame buffer of the receiver is used to queue frames of the application for display. A frame rate associated with rendering at least one next frame of the application is adjusted using the one or more performance metrics of the receiver to control population of the frame buffer. Subsequent frames of the application hosted by the server are rendered using the adjusted frame rate. Upon rendering the subsequent frames, the server sends the subsequent frames to the receiver for display.Type: GrantFiled: March 25, 2022Date of Patent: July 11, 2023Assignee: Nvidia CorporationInventors: Rouslan Dimitrov, Viktor Grigoryevich Vandanov, Sau Yan Keith Li, James Howard, Scott Phillip Cutler
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Publication number: 20230213999Abstract: A computer-implemented method of controlling power consumption in a multi-processor computing device comprises determining a first value for a first power setting associated with a first processor based on a sound level generated by the multi-processor computing device; determining a second value for the first power setting based on a power consumption level of the multi-processor computing device; comparing the first value to the second value; and causing the first processor to perform one or more operations based on the lesser of the first value and the second value.Type: ApplicationFiled: October 6, 2022Publication date: July 6, 2023Inventors: Thomas E. Dewey, Michael IRWIN, Simon LAI, Sau Yan Keith LI
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Publication number: 20230213996Abstract: A computer-implemented method of controlling power consumption in a multi-processor computing device, the method comprises: determining a target sound level for the multi-processor computing device; determining one or more candidate fan speed combinations for a first fan associated with a first temperature-controlled device included in the multi-processor computing device and a second fan associated with a second temperature-controlled device included in the multi-processor computing device based on the target sound level; determining a temperature error for one of the first temperature-controlled device, the second temperature-controlled device, or a third temperature-controlled device included in the multi-processor computing device based on the one or more candidate fan speed combinations and a measured temperature value for one of the first temperature-controlled device, the second temperature-controlled device, or the third temperature-controlled device; determining a value for a first power setting assoType: ApplicationFiled: October 6, 2022Publication date: July 6, 2023Inventors: Thomas E. DEWEY, Michael IRWIN, Simon LAI, Sau Yan Keith LI
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Publication number: 20230214000Abstract: A computer-implemented method of controlling power consumption in a multi-processor computing device comprises: determining whether a first processor is operating in a high-power regime or a low-power regime; selecting a first set of control rules that includes a first subset of control rules that apply when the first processor is operating in the high-power regime and a second subset of control rules that apply when the first processor is operating in the low-power regime; determining one or more power settings for the first processor based on the first set of control rules; and causing the first processor to perform one or more operations based on the one or more power settings.Type: ApplicationFiled: October 6, 2022Publication date: July 6, 2023Inventors: Thomas E. DEWEY, Michael IRWIN, Simon LAI, Sau Yan Keith LI
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Publication number: 20230087268Abstract: A weighted average execution time associated with each execution stage of a plurality of execution stages used to process a plurality of frames in parallel is obtained. The processing of each of the plurality of frames is performed at each of the plurality of execution stages in a sequential order, starting with an initial execution stage and continuing with each subsequent execution stage. A first largest weighted average execution time associated with one of the plurality of execution stages is determined. A delay to the initial execution stage prior to processing a first next frame is applied. The delay is determined based on the first largest weighted average execution time.Type: ApplicationFiled: September 21, 2021Publication date: March 23, 2023Inventors: Sau Yan Keith Li, Seth Schneider, Cody Robson, Lars Nordskog, Charles Hansen, Rouslan Dimitrov
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Publication number: 20220222783Abstract: Embodiments of the present invention provide end-to-end frame time synchronization designed to improve smoothness for displaying images of 3D applications, such as PC gaming applications. Traditionally, an application that renders 3D graphics functions based on the assumption that the average render time will be used as the animation time for a given frame. When this condition is not met, and the render time for a frame does not match the average render time of prior frames, the frames are not captured or displayed at a consistent rate. This invention enables feedback to be provided to the rendering application for adjusting the animation times used to produce new frames, and a post-render queue is used to store completed frames for mitigating stutter and hitches. Flip control is used to sync the display of a rendered frame with the animation time used to generate the frame, thereby producing a smooth, consistent image.Type: ApplicationFiled: March 28, 2022Publication date: July 14, 2022Inventors: Thomas Albert Petersen, Ankan Banerjee, Shishir Goyal, Sau Yan Keith Li, Lars Nordskog, Rouslan Dimitrov
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Patent number: 11321816Abstract: Embodiments of the present invention provide end-to-end frame time synchronization designed to improve smoothness for displaying images of 3D applications, such as PC gaming applications. Traditionally, an application that renders 3D graphics functions based on the assumption that the average render time will be used as the animation time for a given frame. When this condition is not met, and the render time for a frame does not match the average render time of prior frames, the frames are not captured or displayed at a consistent rate. This invention enables feedback to be provided to the rendering application for adjusting the animation times used to produce new frames, and a post-render queue is used to store completed frames for mitigating stutter and hitches. Flip control is used to sync the display of a rendered frame with the animation time used to generate the frame, thereby producing a smooth, consistent image.Type: GrantFiled: February 17, 2021Date of Patent: May 3, 2022Assignee: NVIDIA CORPORATIONInventors: Thomas Albert Petersen, Ankan Banerjee, Shishir Goyal, Sau Yan Keith Li, Lars Nordskog, Rouslan Dimitrov
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Publication number: 20210255680Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.Type: ApplicationFiled: May 3, 2021Publication date: August 19, 2021Inventors: Sau Yan Keith LI, Thomas E. DEWEY, Arthur CHEN, Simon LAI, Amit PABALKAR, Santosh NAYAK
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Publication number: 20210243101Abstract: A display device for measuring the end-to-end latency of a computing system. The computing system includes an input device, a computing device, and the display device. The display device is directly connected with the input device and receives input data packets generated by the input device in response to received user input events. The display device passes the input packets to the computing device for graphics processing. The display device measures the end-to-end latency comprising the sum of three latencies. A first latency comprises an input delay of the input device. A second latency comprises an amount of time between generation of the input packet and a corresponding change in pixel values caused by the input event at the display device. A third latency comprises a display latency. The display device also displays latency information associated with the measured end-to-end latency.Type: ApplicationFiled: June 4, 2020Publication date: August 5, 2021Inventors: Joohwan Kim, Benjamin Boudaoud, Josef B. Spjut, Morgan S. McGuire, Seth P. Schneider, Rouslan L. Dimitrov, Lars Nordskog, Cody J. Robson, Sau Yan Keith Li, Gerrit Ary Slavenburg, Tom J. Verbeure
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Publication number: 20210174475Abstract: Embodiments of the present invention provide end-to-end frame time synchronization designed to improve smoothness for displaying images of 3D applications, such as PC gaming applications. Traditionally, an application that renders 3D graphics functions based on the assumption that the average render time will be used as the animation time for a given frame. When this condition is not met, and the render time for a frame does not match the average render time of prior frames, the frames are not captured or displayed at a consistent rate. This invention enables feedback to be provided to the rendering application for adjusting the animation times used to produce new frames, and a post-render queue is used to store completed frames for mitigating stutter and hitches. Flip control is used to sync the display of a rendered frame with the animation time used to generate the frame, thereby producing a smooth, consistent image.Type: ApplicationFiled: February 17, 2021Publication date: June 10, 2021Inventors: Thomas Albert Petersen, Ankan Banerjee, Shishir Goyal, Sau Yan Keith Li, Lars Nordskog, Rouslan Dimitrov
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Patent number: 10996725Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.Type: GrantFiled: August 21, 2018Date of Patent: May 4, 2021Assignee: NVIDIA CorporationInventors: Sau Yan Keith Li, Thomas E. Dewey, Arthur Chen, Simon Lai, Amit Pabalkar, Santosh Nayak
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Patent number: 10957020Abstract: Embodiments of the present invention provide end-to-end frame time synchronization designed to improve smoothness for displaying images of 3D applications, such as PC gaming applications. Traditionally, an application that renders 3D graphics functions based on the assumption that the average render time will be used as the animation time for a given frame. When this condition is not met, and the render time for a frame does not match the average render time of prior frames, the frames are not captured or displayed at a consistent rate. This invention enables feedback to be provided to the rendering application for adjusting the animation times used to produce new frames, and a post-render queue is used to store completed frames for mitigating stutter and hitches. Flip control is used to sync the display of a rendered frame with the animation time used to generate the frame, thereby producing a smooth, consistent image.Type: GrantFiled: December 3, 2018Date of Patent: March 23, 2021Assignee: NVIDIA CORPORATIONInventors: Thomas Albert Petersen, Ankan Banerjee, Shishir Goyal, Sau Yan Keith Li, Lars Nordskog, Rouslan Dimitrov
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Patent number: 10740254Abstract: Embodiments of the present invention may be directed to a graphics system of a computer system. The system may include a frame buffer having a number of partitions respectively mapped to a number of discrete memory devices and a dedicated copy buffer operable to store new image frames, mapped to a first memory device. The first memory device corresponds to a first partition of the number of partitions. The system may also include a loader circuit coupled between the frame buffer and the dedicated copy buffer, operable to copy new image frames from the frame buffer to the dedicated copy buffer. The system may also include a clocked output coupled to receive an image frame from the dedicated copy buffer and operable to drive a display device therewith. The system may enter a low power state wherein a number of the discrete memory devices are powered off.Type: GrantFiled: May 18, 2012Date of Patent: August 11, 2020Assignee: NVIDIA CORPORATIONInventors: Christopher Thomas Cheng, Sau Yan Keith Li, Thomas Edward Dewey, Franciscus W. Sijstermans
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Publication number: 20200064894Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.Type: ApplicationFiled: August 21, 2018Publication date: February 27, 2020Inventors: Sau Yan Keith LI, Thomas E. DEWEY, Arthur CHEN, Simon LAI, Amit PABALKAR, Santosh NAYAK
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Publication number: 20190172181Abstract: Embodiments of the present invention provide end-to-end frame time synchronization designed to improve smoothness for displaying images of 3D applications, such as PC gaming applications. Traditionally, an application that renders 3D graphics functions based on the assumption that the average render time will be used as the animation time for a given frame. When this condition is not met, and the render time for a frame does not match the average render time of prior frames, the frames are not captured or displayed at a consistent rate. This invention enables feedback to be provided to the rendering application for adjusting the animation times used to produce new frames, and a post-render queue is used to store completed frames for mitigating stutter and hitches. Flip control is used to sync the display of a rendered frame with the animation time used to generate the frame, thereby producing a smooth, consistent image.Type: ApplicationFiled: December 3, 2018Publication date: June 6, 2019Inventors: Thomas Albert Petersen, Ankan Banerjee, Shishir Goyal, Sau Yan Keith Li, Lars Nordskog, Rouslan Dimitrov