Abstract: A method for performing a write operation includes selecting, by a host, at least a free write buffer from a plurality of write buffers of a shared memory buffer (SMB) by accessing a cache structure within the SMB for tracking the free write buffer; sending, by the host, at least a logical address accessed from the cache structure with respect to the selected write buffer to issue a write-command to a non-volatile memory; receiving a locking instruction of the selected write buffer from the non-volatile memory; updating a status of the selected write buffer within the cache structure based on the received locking instruction; and allowing the non-volatile memory to extract contents of one or more locked write buffers including the selected write buffer.

Abstract: A method for offloading a lookup operation to a NAND offload apparatus, including receiving, by the NAND offload apparatus, a NAND read command from a key-value solid-state drive (KV SSD) NAND interface, wherein the NAND offload apparatus is connected between the KV SSD NAND interface and a NAND device using a NAND bus; determining whether the NAND read command includes an information element indicating an indirect read operation; based on the NAND read command including the information element, performing the indirect read operation by the NAND offload apparatus; and based on the NAND read command not including the information element: passing, by the NAND offload apparatus, the NAND read command to the NAND device through the NAND bus, and configuring, by the NAND offload apparatus, a switch an output gate to pass a response message from the NAND device to the KV SSD NAND interface.

Abstract: A method of operating a non-volatile memory device is provided. The device includes a latch, a page buffer and blocks, each of which includes pages. The method includes: receiving a page command for a write operation corresponding to a page of one of the blocks; receiving a write command for writing data to the page buffer; latching preexisting latched data or random data generated as latched data; writing the latched data to a page of a new block from among the plurality of blocks that corresponds to a page address based on the write command; and repeatedly updating the page address and repeatedly writing the latched data to additional pages corresponding to each updated page address until each page of the new block has been written to.

Abstract: The present disclosure provides a method of logical to physical mapping for a data-storage device comprising a non-volatile memory device. The method comprises maintaining a first type of information representing at least a part of a logical-to-physical address translation map. Further, the method comprises maintaining a second type of information pertaining to the logical-to-physical translation map as a part of a physical page. Further, the method comprises completing a logical-to-physical mapping based on the first and second type of information to thereby determine a physical location, within one or more of the physical pages, of the data stored in each logical page.

Abstract: Embodiments herein disclose a method for managing seed value for data scrambling in a NAND memory. The method includes detecting, by a NAND controller, a first scrambling of the data of a word line in the NAND memory. The method further includes caching, by the NAND controller, at least one of a last written data of the word line post the first scrambling for each open block in a Dynamic Random Access Memory (DRAM) for programming the word line, and a super page of the last written data of the word line in the DRAM for programming the super page. The method can be used to manage the seed value which is used for NAND page scrambling, which can reduce retention effect. As a result, the retention recycles for the NAND cells may be reduced, which may improve endurance.

Abstract: A method for performing a write operation includes selecting, by a host, at least a free write buffer from a plurality of write buffers of a shared memory buffer (SMB) by accessing a cache structure within the SMB for tracking the free write buffer; sending, by the host, at least a logical address accessed from the cache structure with respect to the selected write buffer to issue a write-command to a non-volatile memory; receiving a locking instruction of the selected write buffer from the non-volatile memory; updating a status of the selected write buffer within the cache structure based on the received locking instruction; and allowing the non-volatile memory to extract contents of one or more locked write buffers including the selected write buffer.

Abstract: The present disclosure provides a method of logical to physical mapping for a data-storage device comprising a non-volatile memory device. The method comprises maintaining a first type of information representing at least a part of a logical-to-physical address translation map. Further, the method comprises maintaining a second type of information pertaining to the logical-to-physical translation map as a part of a physical page. Further, the method comprises completing a logical-to-physical mapping based on the first and second type of information to thereby determine a physical location, within one or more of the physical pages, of the data stored in each logical page.

Abstract: Embodiments herein disclose a method for managing seed value for data scrambling in a NAND memory. The method includes detecting, by a NAND controller, a first scrambling of the data of a word line in the NAND memory. The method further includes caching, by the NAND controller, at least one of a last written data of the word line post the first scrambling for each open block in a Dynamic Random Access Memory (DRAM) for programming the word line, and a super page of the last written data of the word line in the DRAM for programming the super page. The method can be used to manage the seed value which is used for NAND page scrambling, which can reduce retention effect. As a result, the retention recycles for the NAND cells may be reduced, which may improve endurance.

Abstract: A method for offloading a lookup operation to a NAND offload apparatus, including receiving, by the NAND offload apparatus, a NAND read command from a key-value solid-state drive (KV SSD) NAND interface, wherein the NAND offload apparatus is connected between the KV SSD NAND interface and a NAND device using a NAND bus; determining, by the NAND offload apparatus, whether the NAND read command includes an information element indicating an indirect read operation; based on determining that the NAND read command includes the information element, performing the indirect read operation by the NAND offload apparatus; and based on determining that the NAND read command does not include the information element: passing, by the NAND offload apparatus, the NAND read command to the NAND device through the NAND bus, and configuring, by the NAND offload apparatus, a switch an output gate to pass a response message from the NAND device to the KV SSD NAND interface.

Abstract: The disclosure relates in some aspects to suspending a read for a non-volatile memory (NVM) device. For example, a lower priority read may be suspended to enable a higher priority read to occur. Once the higher priority read completes, the lower priority read is resumed. To improve the efficiency of the read suspension, the lower priority read may be suspended once data sensing at a current level of the NVM device completes. The data for each level that has already been sensed is then stored so that this data does not need to be sensed again. Once the lower priority read is resumed, the data sensing starts at the next level of the NVM device. The data output for the lower priority read thus includes the stored data for any levels read before the read is suspended, along with the data from the levels read after the read is resumed.

Abstract: Aspects of the disclosure provide for management of a flash translation layer (FTL) for a non-volatile memory (NVM) in a Solid State Drive (SSD). The methods and apparatus provide a logical to physical (L2P) table where a first portion of the table is used for mapping frequently accessed hot data to a first subdrive in the NVM. Additionally, a second portion of the L2P table is provided for mapping cold data less frequently accessed than the hot data to a second subdrive, where logical blocks for storing the cold data in the second subdrive are larger than logical blocks storing the hot data in the first subdrive. Separation of the L2P table into hot and cold subdrives reduces the L2P table size that is needed in RAM for logical to physical memory mapping, while at the same time provides lower write amplification and latencies, especially for large capacity SSDs.

Abstract: A non-volatile storage apparatus includes a plurality of non-volatile memory cells and control circuitry. The control circuitry is configured to apply one or more soft erase pulses to the plurality of non-volatile memory cells to reduce threshold voltages of the plurality of non-volatile memory cells from initial levels corresponding to programmed data to intermediate levels below the initial levels and above an erased level. The control circuitry is configured to apply one or more soft programming pulse to increase threshold voltages of the plurality of non-volatile memory cells from the intermediate levels to final levels corresponding to the programmed data.

Abstract: Apparatuses and techniques are provided for switching a solid-state device (SSD) between a traditional SSD mode and an open-channel SSD (OCSSD) mode. In one aspect, a set of commands are defined for communicating different types of data from a Flash Translation Layer (FTL) between the host and SSD. The commands can include different predetermined sets of bits which carry different types of FTL data in a standardized format. The commands can be transmitted using reserved data words in an interface specification which interfaces the host to the SSD. The commands can include commands to transfer a logical-to-physical address table, a validity bitmap and a wear table. A switch mode command can include a bit indicating whether the mode is to be switched from traditional SSD to OCSSD, or from OCSSD to traditional SSD.

Abstract: A non-volatile storage apparatus includes a plurality of non-volatile memory cells and control circuitry. The control circuitry is configured to apply one or more soft erase pulses to the plurality of non-volatile memory cells to reduce threshold voltages of the plurality of non-volatile memory cells from initial levels corresponding to programmed data to intermediate levels below the initial levels and above an erased level. The control circuitry is configured to apply one or more soft programming pulse to increase threshold voltages of the plurality of non-volatile memory cells from the intermediate levels to final levels corresponding to the programmed data.

Abstract: Apparatuses and techniques are provided for switching a solid-state device (SSD) between a traditional SSD mode and an open-channel SSD (OCSSD) mode. In one aspect, a set of commands are defined for communicating different types of data from a Flash Translation Layer (FTL) between the host and SSD. The commands can include different predetermined sets of bits which carry different types of FTL data in a standardized format. The commands can be transmitted using reserved data words in an interface specification which interfaces the host to the SSD. The commands can include commands to transfer a logical-to-physical address table, a validity bitmap and a wear table. A switch mode command can include a bit indicating whether the mode is to be switched from traditional SSD to OCSSD, or from OCSSD to traditional SSD.

Abstract: Aspects of the disclosure provide for control of a flash translation layer (FTL) in a non-volatile memory (NVM). Disclosed methods and apparatus provide for receiving a message in the FTL, which is transmitted from a host device, and includes desired recycle ratio information that is determined by the host where the ratio is a number of host writes to a number of recycle writes to be performed by the FTL. Based on the recycle ratio information, the FTL determines a target recycle ratio and performs recycling of memory blocks in the NVM based on the determined target recycle ratio. In this manner, the host device is able to exert control over the recycle ratio utilized in the FTL via a transmitted message, which allows the recycle ratio to be more adaptive to host write conditions known to the host device, but not known in the SSD.

Abstract: Exemplary embodiments provide for compressing, storing, retrieving and decompressing paged code from mass storage devices. By evaluating the size of compressed virtual pages relative to the storage page (read unit) of the mass storage device into which the compressed virtual pages are to be stored, decisions can be made which facilitate later read out and decompression of those compressed virtual pages. According to exemplary embodiments, a virtual page can be stored uncompressed, compressed but undivided or compressed and subdivided into a plurality of parts based on an evaluation.

Abstract: The disclosure relates in some aspects to suspending a read for a non-volatile memory (NVM) device. For example, a lower priority read may be suspended to enable a higher priority read to occur. Once the higher priority read completes, the lower priority read is resumed. To improve the efficiency of the read suspension, the lower priority read may be suspended once data sensing at a current level of the NVM device completes. The data for each level that has already been sensed is then stored so that this data does not need to be sensed again. Once the lower priority read is resumed, the data sensing starts at the next level of the NVM device. The data output for the lower priority read thus includes the stored data for any levels read before the read is suspended, along with the data from the levels read after the read is resumed.

Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to receive a plurality of non-sequential memory access commands directed to the set of non-volatile memory cells, predict a predicted memory access command based on the plurality of non-sequential memory access commands, and access the set of non-volatile memory cells according to the predicted memory access command.

Abstract: Aspects of the disclosure provide for control of a flash translation layer (FTL) in a non-volatile memory (NVM). Disclosed methods and apparatus provide for receiving a message in the FTL, which is transmitted from a host device, and includes desired recycle ratio information that is determined by the host where the ratio is a number of host writes to a number of recycle writes to be performed by the FTL. Based on the recycle ratio information, the FTL determines a target recycle ratio and performs recycling of memory blocks in the NVM based on the determined target recycle ratio. In this manner, the host device is able to exert control over the recycle ratio utilized in the FTL via a transmitted message, which allows the recycle ratio to be more adaptive to host write conditions known to the host device, but not known in the SSD.