Patents by Inventor Saugata DUTTA

Saugata DUTTA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reference buffer
    Patent number: 11646662
    Abstract: A reference voltage generator comprises a comparator, a digital-to-analog converter (DAC) and a switched capacitor accumulator. The comparator receives a reference voltage input, a feedback input, and a control signal. The DAC is coupled to an output of the comparator, and the switched capacitor accumulator is coupled to an output of the DAC. In some implementations, a digital filter is coupled between the output of the comparator and the input of the DAC. The switched capacitor accumulator can be coupled to a buffer that outputs the feedback input and a reference voltage for an analog-to-digital converter (ADC). In some implementations, the feedback loop includes N one-bit DACs coupled to the output of the comparator and N switched capacitor accumulators, each of which is coupled to a unique one-bit DAC.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: May 9, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sabu Paul, Raghu Nandan Srinivasa, Srinivas Bangalore Seshadri, Saugata Dutta
  • REFERENCE BUFFER
    Publication number: 20220352820
    Abstract: A reference voltage generator comprises a comparator, a digital-to-analog converter (DAC) and a switched capacitor accumulator. The comparator receives a reference voltage input, a feedback input, and a control signal. The DAC is coupled to an output of the comparator, and the switched capacitor accumulator is coupled to an output of the DAC. In some implementations, a digital filter is coupled between the output of the comparator and the input of the DAC. The switched capacitor accumulator can be coupled to a buffer that outputs the feedback input and a reference voltage for an analog-to-digital converter (ADC). In some implementations, the feedback loop includes N one-bit DACs coupled to the output of the comparator and N switched capacitor accumulators, each of which is coupled to a unique one-bit DAC.
    Type: Application
    Filed: April 30, 2021
    Publication date: November 3, 2022
    Inventors: Sabu PAUL, Raghu Nandan SRINIVASA, Srinivas Bangalore SESHADRI, Saugata DUTTA