Abstract: A method for compressing a plurality of contiguous addresses for storage in a queue. The method includes recognizing that a first address of the plurality of addresses is an individual address that corresponds to a memory location that is transferred individually. A first value of a block identifier bit is associated with the first address, with the first value identifying the first address as an individual address. The first address and the first value of the block identifier bit are stored into the queue. A further address of the plurality of addresses is recognized as a block address corresponding to a plurality of contiguous data words that reside at a respective plurality of contiguous addresses, that begin with the further address, and that are transferred as a block unit. A second value of the block identifier bit is associated with the further address, the second value identifying the further address as a block address.

Abstract: A "bit-sliced" construction of our cache module dictates dual TAG RAM structures and dual invalidation queues, yielding enhanced performance. By putting half the TAG array in each of two cache arrays, and allowing each to handle only one-half of the possible address values, processor operations and invalidation operations can be "overlapped", and even operate simultaneously.

Abstract: A "bit-sliced" construction cache module dictates dual TAG RAM Structures and dual invalidation queues, yielding enhanced performance: putting half the TAG array in each of two cache arrays, and allowing each to handle only one-half of the possible address values. Preferably, one half-module handles ZERO least-significant bits and the other handles ONE least-significant bits. Processor operations and invalidation operations can be "overlapped", and even operate simultaneously.

Abstract: An Invalidation Queue (IQ) arrangement in a computer system having Main Memory and, Cache-Memory, with a pair of intermediate main-buses this IQ arrangement comprising: a pair of split IQ ASIC Arrays disposed between each Cache-Memory and the main-buses and being adapted to assure identical data in all identical memory addresses in different caches, and to "remember" write-operations along the buses and to execute invalidation sequences for any Cache-Memory unit as dictated by that Cache-Memory unit.

Abstract: By expanding the cache address invalidation queue into bit slices for holding odd invalidation addresses and even invalidation addresses and also by providing a more efficient series of transition cycles to accomplish cache address invalidations both during a cache hit or a cache miss cycle, the present architecture and methodology permits a faster cycle of cache address invalidations when required and also permits a higher frequency of processor access to cache without the processor being completely locked out from cache memory access during heavy traffic and high level of cache invalidation conditions.

Abstract: A system and circuitry is provided by which certain selected embedded pins of an integrated circuit gate array may be provided with dual functions, that is to say, they may act either as receivers of an externally sourced input signal or as transmitters of an internally generated output signal. Each selected input/output pin is controlled by an associated flip-flop residing in a chain of flip-flops so that an associated flip-flop will determine the condition of two buffer-drivers attached to each input/output pin. While the first buffer-driver is tri-stated (disabled), then the embedded pin operates as an input receiving function. When the first buffer-driver is enabled, the embedded I/O pin operates as the conveyer of an output signal from the internal output logic.

Abstract: A method and implementation is supplied for the synchronous loading and integrity checking of registers located in two different integrated circuit chips. Thus in a computer system having cache memory where the cache memory is sliced into two portions, one of which holds even addresses and the other of which holds odd addresses, there is provided two individual chips each of which has a program word address register which is loaded at the exact same period of time and which is additionally incremented in both cases at the exact same period of time. Further means are provided for checking the integrity of the program word address registers in the first slice and the second slice of the cache in order to insure that they are coherent, or if not coherent, then a disable signal will prevent usage of the address data involved.

Abstract: A processor cache memory system utilizes separate cache controllers for independently managing even and odd input address requests with the even and odd address requests being mapped into the respective controllers. Each cache controller includes tag RAM for storing address tags, including a field for storing the least significant address bit, so that the stored tags distinguish between the odd and even addresses. Upon failure of a cache controller, both the even and odd addresses are directed to the operational controller and the stored least significant bit address tag distinguishes between the odd and even input addresses to appropriately generate HIT/MISS signals. The controllers include block address counter logic for generating respective even and odd invalidation addresses for simultaneously performing invalidation cycles thereon when both controllers are operational.

Abstract: In a time-shared bus computer system with processors having cache memories, an adjustable invalidation queue for use in the cache memories. The invalidation queue has adjustable upper and lower limit positions that define when the queue is logically full and logically empty, respectively. The queue is flushed down to the lower limit when the contents of the queue attain the upper limit. During the queue flushing operation, WRITE requests on the bus are RETRYed. The computer maintenance system sets the upper and lower limits at system initialization time to optimize system performance under maximum bus traffic conditions.

Abstract: A message transfer system between multiple processors in a network. Each processor includes an interprocessor communications (IPC) hardware unit having an unique address count. An address count generator in a designated IPC hardware unit generates a sequence of binary count numbers such that when the generated count number matches the address of the IPC hardware unit, then that particular hardware unit and its associated processor are granted a time period of bus access for sending messages on the IPC network bus to other processors. Messages on the IPC network bus can be received by an IPC hardware unit at any time irrespective of the generated count number. Any sending processor that has bus access can concurrently provide multiple messages where each of the multiple messages is directed to each particular processor for reception. Thus one sender, with bus access, can communicate with multiple receivers during its transmission onto the IPC network bus connecting the processors.

Abstract: In a digital data transfer system whereby a plurality of driver units are all connected to and share the same common system bus, there is provided control gating logic which will prevent the enablement of a subsequent driver for a fixed delay time until it is certain that the previous driver has been shut down. Due to switching time variations in driving units, a fixed delay time is set to function in a first driver that is beginning its data transmission to be sure that another driver which was previously transmitting data has been completely turned-off before the first driver gains access to the commonly shared bus. This ensures that no two drivers can simultaneously be driving data onto the system bus at the same time which would obviate the integrity of data transmitted.

Abstract: An automatic re-configurable computer system having a standard processor module and standard main memory and I/O control modules where each module is inter-connected to a common system bus. Automatic re-configuration occurs in the standard modules, when an optional module is connected onto the system bus, permitting inter-cooperation between the standard and optional modules to take place.

Abstract: Arbitration and control circuitry for monitoring the two processors sharing a system bus to insure fair access to system resources and to sense error conditions which occur in order to hold access for the processor involved until the error condition is cleared. The arbitration circuitry provides for two levels of bus access requests where one level involves normal requests and a second level involves priority request which take precedence over normal requests.

Abstract: A programmable array logic unit (PAL) having a disconnected array of gates, inverters and D-Type flip-flops, is utilized by burning-in the interconnections, to enable the D flip-flops to function as J-K flip-flops and/or toggle flip-flops to enable flexibility in the functions available for utilization, by providing inputs for Direct Set, Direct Clear and Hold.

Abstract: A method and technique for inserting additive logic into the architecture of a gate array chip package whereby spare input and output pins can later be used to alter the logic functions by either disabling or enabling certain logic units internal to the chip by external signal injection.

Abstract: A method and technique for inserting additive logic and flip-flops into the architecture of a gate array chip package whereby spare input and output pins can later be used to alter the logic functions by either disabling or enabling certain logic units internal to the chip by external signal injection.

Abstract: A system wherein multiple sources of data each have drivers for transmitting data to a common system bus. The drivers are each managed by individual enabling logic which is controlled by a flip-flop driven by a clock. Thus no driver can connect and drive data onto the bus until one clock period after the previously connected driver has been disabled and disconnected from the bus.