Abstract: A semiconductor-superconductor hybrid device comprises a semiconductor component having first and second terminals, first and second gate electrodes for electrostatically gating the first and second terminals. A second gate electrode electrostatically gates the second terminal, and a superconductor component is configured for energy level hybridisation with the semiconductor component. A method of measuring a non-local conductance of the semiconductor component comprises applying a first gate voltage to the first gate electrode to gate the first terminal to an open regime, applying a second gate voltage to the second gate electrode to gate the second terminal to a tunnelling regime, applying a bias voltage to the first terminal, and while applying the first gate voltage, the second gate voltage, and the bias voltage, measuring a current through the second terminal; with the superconductor component grounded.

Abstract: A method of selectively etching a metal component of a workpiece further comprising a ferromagnetic insulator component. The method comprises contacting the metal component with an etchant solution. The etchant solution comprises a basic etchant and a solvent. The method is useful in the context of the fabrication of semiconductor-superconductor-ferromagnetic insulator hybrid devices, for example. The etchant solution may not attack the ferromagnetic insulator component. Also provided is a composition for etching a metal, and a kit comprising the composition and a composition for depositing a styrene-acrylate co-polymer on a surface.

Abstract: A semiconductor-ferromagnetic insulator-superconductor hybrid device comprises a semiconductor component, a ferromagnetic insulator component, and a superconductor component. The semiconductor component has at least three facets. The ferromagnetic insulator component is arranged on a first facet and a second facet. The superconductor component is arranged on a third facet and extends over the ferromagnetic insulator component on at least the second facet. The device is useful for generating Majorana zero modes, which are useful for quantum computing. Also provided are a method of fabricating the device, and a method of inducing topological behaviour in the device.

Abstract: The disclosure relates to a quantum device and method of fabricating the same. The device comprises one or more semiconductor-superconductor nanowires, each comprising a length of semiconductor material and a coating of superconductor material coated on the semiconductor material. The nanowires may be formed over a substrate. In a first aspect at least some of the nanowires are full-shell nanowires with superconductor material being coated around a full perimeter of the semiconductor material along some or all of the length of the wire, wherein the device is operable to induce at least one Majorana zero mode, MZM, in one or more active ones of the full-shell nanowires. In a second aspect at least some of the nanowires are arranged vertically relative to the plane of the substrate in the finished device.

Abstract: The disclosure relates to a quantum device and method of fabricating the same. The device comprises one or more semiconductor-superconductor nanowires, each comprising a length of semiconductor material and a coating of superconductor material coated on the semiconductor material. The nanowires may be formed over a substrate. In a first aspect at least some of the nanowires are full-shell nanowires with superconductor material being coated around a full perimeter of the semiconductor material along some or all of the length of the wire, wherein the device is operable to induce at least one Majorana zero mode, MZM, in one or more active ones of the full-shell nanowires. In a second aspect at least some of the nanowires are arranged vertically relative to the plane of the substrate in the finished device.

Abstract: The disclosure relates to a quantum device and method of fabricating the same. The device comprises one or more semiconductor-superconductor nanowires, each comprising a length of semiconductor material and a coating of superconductor material coated on the semiconductor material. The nanowires may be formed over a substrate. In a first aspect at least some of the nanowires are full-shell nanowires with superconductor material being coated around a full perimeter of the semiconductor material along some or all of the length of the wire, wherein the device is operable to induce at least one Majorana zero mode, MZM, in one or more active ones of the full-shell nanowires. In a second aspect at least some of the nanowires are arranged vertically relative to the plane of the substrate in the finished device.