Patents by Inventor Saurabh Agrawal

Saurabh Agrawal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8154911
    Abstract: A memory device includes bitlines, wordlines and a matrix of memory cells arranged in rows and columns. Each of the bitlines is electrically connected to memory cells in one of the columns. Each of the wordlines is electrically connected to memory cells in one of the rows. A bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: April 10, 2012
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventors: Naveen Batra, Rajiv Kumar, Saurabh Agrawal
  • Publication number: 20110149662
    Abstract: A memory device includes bitlines, wordlines and a matrix of memory cells arranged in rows and columns. Each of the bitlines is electrically connected to memory cells in one of the columns. Each of the wordlines is electrically connected to memory cells in one of the rows. A bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline.
    Type: Application
    Filed: April 19, 2010
    Publication date: June 23, 2011
    Applicant: STMICROELECTRONICS Pvt. Ltd.
    Inventors: Naveen BATRA, Rajiv Kumar, Saurabh Agrawal
  • Publication number: 20080292531
    Abstract: A method of cutting, thinning, welding and chemically functionalizing multiwalled carbon nanotubes (CNTs) with carboxyl and allyl moieties, and altering the electrical properties of the CNT films by applying high current densities combined with air-exposure is developed and demonstrated. Such welded high-conductance CNT networks of functionalized CNTs could be useful for device and sensor applications, and may serve as high mechanical toughness mat fillers that are amenable to integration with nanocomposite matrices.
    Type: Application
    Filed: October 18, 2007
    Publication date: November 27, 2008
    Inventors: Ramanath GANAPATHIRAMAN, Saurabh AGRAWAL, Raghuveer S. MAKALA
  • Publication number: 20080089829
    Abstract: Controllably aligned carbon nanotubes are grown, without the use of a predeposition catalyst, on electrically conducting templates that form an electrical contact with the nanotubes. The method allows fabrication of nanotube-based devices with built-in back-side electrical contacts on silicon and other substrate surfaces.
    Type: Application
    Filed: October 13, 2006
    Publication date: April 17, 2008
    Inventors: Ramanath Ganapathiraman, Saurabh Agrawal, Matthew J. Frederick, Raghuveer Makala
  • Publication number: 20070035226
    Abstract: Hybrid structures include aligned carbon nanotube bundles grown on curved surfaces such as micro sized or nano sized particles or bulk substrates having micro size or nano sized protrusions. The morphology of the hybrid structures can controlled by varying the size and packing of the particles or protrusions.
    Type: Application
    Filed: March 21, 2006
    Publication date: February 15, 2007
    Inventors: Ramanath Ganapathiraman, Saurabh Agrawal