Patents by Inventor SAURABH CHADHA
SAURABH CHADHA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11237606Abstract: In an example, a computer system includes: a hardware platform including a processor, system memory, and a plurality of input/output (IO) devices, the processor including a controller having a trace and optimize function controller (TOF); and a software platform including an operating system (OS) executing on the hardware platform; wherein the TOF is configured to communicate with the processor, the system memory, and the plurality of IO devices to obtain current settings thereof and to determine final settings for the processor, the system memory, and the plurality of IO devices based on the current settings; and wherein the controller is configured to control the processor, the system memory, and the plurality of IO devices based on the final settings.Type: GrantFiled: March 8, 2019Date of Patent: February 1, 2022Assignee: International Business Machines CorporationInventors: Anil Bindu Lingambudi, Diyanesh B. Chinnakkonda Vidyapoornachary, Saurabh Chadha
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Patent number: 11119890Abstract: A computer-implemented method for instruction-level tracing for analyzing processor failure includes detecting a failure during operation of a processor circuit. The method further includes parsing a miscompare trace to determine a plurality of opcodes executed by the processor prior to the failure. The method further includes generating a workload comprising a set of opcodes by filtering the set of opcodes from the miscompare trace. The method further includes performing a consistency check of the workload to determine a commit ratio of the workload, the commit ratio indicative of a number of times the failure occurs when the workload is executed a predetermined number of times. The method further includes using the workload for debugging the failure based on the commit ratio being above a predetermined threshold.Type: GrantFiled: August 28, 2019Date of Patent: September 14, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Saurabh Chadha, Daniel Lewis, Diyanesh B. Chinnakkonda Vidyapoornachary
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Patent number: 10997029Abstract: An apparatus for core repair includes a failure analysis and recovery (“FAR”) probe that accesses a core of a processor and units of the core over a low-level communication bus while the core is operational after a failure notification. The FAR probe compares operational data of the core versus vital product data (“VPD”) while the core is running tests and a thermal, power, functional (“TPF”) workload to determine if the core is in a degraded state and runs tests to identify a failure after determining that the core is in a degraded state. The FAR probe adjusts parameters of the core in response to identifying a failure of the core and re-evaluates the core to determine if the core is functional. The FAR probe returns the core to service after determining that the core is functional. The FAR probe operates independent of other processor cores while the cores are operational.Type: GrantFiled: March 7, 2019Date of Patent: May 4, 2021Assignee: International Business Machines CorporationInventors: Rocio Yolanda Garza, Tony Sawan, Saurabh Chadha, Diyanesh B. Chinnakkonda Vidyapoornachary
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Publication number: 20210064513Abstract: A computer-implemented method for instruction-level tracing for analyzing processor failure includes detecting a failure during operation of a processor circuit. The method further includes parsing a miscompare trace to determine a plurality of opcodes executed by the processor prior to the failure. The method further includes generating a workload comprising a set of opcodes by filtering the set of opcodes from the miscompare trace. The method further includes performing a consistency check of the workload to determine a commit ratio of the workload, the commit ratio indicative of a number of times the failure occurs when the workload is executed a predetermined number of times. The method further includes using the workload for debugging the failure based on the commit ratio being above a predetermined threshold.Type: ApplicationFiled: August 28, 2019Publication date: March 4, 2021Inventors: Saurabh Chadha, Daniel Lewis, Diyanesh B. Chinnakkonda Vidyapoornachary
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Publication number: 20200285540Abstract: An apparatus for core repair includes a failure analysis and recovery (“FAR”) probe that accesses a core of a processor and units of the core over a low-level communication bus while the core is operational after a failure notification. The FAR probe compares operational data of the core versus vital product data (“VPD”) while the core is running tests and a thermal, power, functional (“TPF”) workload to determine if the core is in a degraded state and runs tests to identify a failure after determining that the core is in a degraded state. The FAR probe adjusts parameters of the core in response to identifying a failure of the core and re-evaluates the core to determine if the core is functional. The FAR probe returns the core to service after determining that the core is functional. The FAR probe operates independent of other processor cores while the cores are operational.Type: ApplicationFiled: March 7, 2019Publication date: September 10, 2020Inventors: ROCIO Yolanda GARZA, Tony Sawan, Saurabh Chadha, Diyanesh B. Chinnakkonda Vidyapoornachary
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Publication number: 20200285288Abstract: In an example, a computer system includes: a hardware platform including a processor, system memory, and a plurality of input/output (IO) devices, the processor including a controller having a trace and optimize function controller (TOF); and a software platform including an operating system (OS) executing on the hardware platform; wherein the TOF is configured to communicate with the processor, the system memory, and the plurality of IO devices to obtain current settings thereof and to determine final settings for the processor, the system memory, and the plurality of IO devices based on the current settings; and wherein the controller is configured to control the processor, the system memory, and the plurality of IO devices based on the final settings.Type: ApplicationFiled: March 8, 2019Publication date: September 10, 2020Inventors: Anil Bindu LINGAMBUDI, Diyanesh B. CHINNAKKONDA VIDYAPOORNACHARY, Saurabh CHADHA
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Patent number: 10409352Abstract: Methods, apparatuses, and products for budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements (‘ITEs’), each ITE having power utilization information indicating an average power consumption of the ITE, including: determining, by a chassis management module, a total power requirement value based on a sum of the average power consumption for each ITE; increasing, by the chassis management module, the total power requirement value in dependence upon a predetermined power utilization delta; identifying, by the chassis management module, one or more power supplies to provide power to the ITEs in the chassis environment in dependence upon power delivery capabilities of the one or more power supplies and the total power requirement value; and powering on the identified one or more power supplies by the chassis management module.Type: GrantFiled: October 30, 2017Date of Patent: September 10, 2019Assignee: International Business Machines CorporationInventors: Saurabh Chadha, Prasanna Jayaraman, Tony E. Sawan
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Publication number: 20180046237Abstract: Methods, apparatuses, and products for budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements (‘ITEs’), each ITE having power utilization information indicating an average power consumption of the ITE, including: determining, by a chassis management module, a total power requirement value based on a sum of the average power consumption for each ITE; increasing, by the chassis management module, the total power requirement value in dependence upon a predetermined power utilization delta; identifying, by the chassis management module, one or more power supplies to provide power to the ITEs in the chassis environment in dependence upon power delivery capabilities of the one or more power supplies and the total power requirement value; and powering on the identified one or more power supplies by the chassis management module.Type: ApplicationFiled: October 30, 2017Publication date: February 15, 2018Inventors: SAURABH CHADHA, PRASANNA JAYARAMAN, TONY E. SAWAN
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Patent number: 9841800Abstract: Methods, apparatuses, and products for budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements (‘ITEs’), each ITE having power utilization information indicating an average power consumption of the ITE, including: determining, by a chassis management module, a total power requirement value based on a sum of the average power consumption for each ITE; increasing, by the chassis management module, the total power requirement value in dependence upon a predetermined power utilization delta; identifying, by the chassis management module, one or more power supplies to provide power to the ITEs in the chassis environment in dependence upon power delivery capabilities of the one or more power supplies and the total power requirement value; and powering on the identified one or more power supplies by the chassis management module.Type: GrantFiled: August 25, 2015Date of Patent: December 12, 2017Assignee: International Business Machines CorporationInventors: Saurabh Chadha, Prasanna Jayaraman, Tony E. Sawan
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Patent number: 9454200Abstract: Methods, apparatuses, and products for budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements (‘ITEs’), each ITE having power utilization information indicating an average power consumption of the ITE, including: determining, by a chassis management module, a total power requirement value based on a sum of the average power consumption for each ITE; increasing, by the chassis management module, the total power requirement value in dependence upon a predetermined power utilization delta; identifying, by the chassis management module, one or more power supplies to provide power to the ITEs in the chassis environment in dependence upon power delivery capabilities of the one or more power supplies and the total power requirement value; and powering on the identified one or more power supplies by the chassis management module.Type: GrantFiled: May 5, 2014Date of Patent: September 27, 2016Assignee: International Business Machines CorporationInventors: Saurabh Chadha, Prasanna Jayaraman, Tony E. Sawan
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Patent number: 9405468Abstract: A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.Type: GrantFiled: May 13, 2014Date of Patent: August 2, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Venkatraghavan Bringivijayaraghavan, Saurabh Chadha, Abhijit Saurabh, Saravanan Sethuraman, Kenneth L. Wright
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Patent number: 9400602Abstract: A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.Type: GrantFiled: August 20, 2014Date of Patent: July 26, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Venkatraghavan Bringivijayaraghavan, Saurabh Chadha, Abhijit Saurabh, Saravanan Sethuraman, Kenneth L. Wright
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Patent number: 9389974Abstract: Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The problem is determined to be associated with a primary driver module in the stacked memory device. In response, the primary driver module is disabled and an emergency driver module is enabled. Each of the plurality of slave memory chips are selected using a multiplexing unit to retrieve data using the emergency driver module.Type: GrantFiled: August 19, 2014Date of Patent: July 12, 2016Assignee: International Business Machines CorporationInventors: Saurabh Chadha, Hillery C. Hunter, Kyu-hyoun Kim, Abhijit Saurabh, Saravanan Sethuraman, Kenneth L. Wright
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Patent number: 9389972Abstract: Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The problem is determined to be associated with a primary driver module in the stacked memory device. In response, the primary driver module is disabled and an emergency driver module is enabled. Each of the plurality of slave memory chips are selected using a multiplexing unit to retrieve data using the emergency driver module.Type: GrantFiled: May 13, 2014Date of Patent: July 12, 2016Assignee: International Business Machines CorporationInventors: Saurabh Chadha, Hillery C. Hunter, Kyu-hyoun Kim, Abhijit Saurabh, Saravanan Sethuraman, Kenneth L. Wright
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Publication number: 20150362971Abstract: Methods, apparatuses, and products for budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements (‘ITEs’), each ITE having power utilization information indicating an average power consumption of the ITE, including: determining, by a chassis management module, a total power requirement value based on a sum of the average power consumption for each ITE; increasing, by the chassis management module, the total power requirement value in dependence upon a predetermined power utilization delta; identifying, by the chassis management module, one or more power supplies to provide power to the ITEs in the chassis environment in dependence upon power delivery capabilities of the one or more power supplies and the total power requirement value; and powering on the identified one or more power supplies by the chassis management module.Type: ApplicationFiled: August 25, 2015Publication date: December 17, 2015Inventors: SAURABH CHADHA, PRASANNA JAYARAMAN, TONY E. SAWAN
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Publication number: 20150331767Abstract: A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.Type: ApplicationFiled: August 20, 2014Publication date: November 19, 2015Inventors: Venkatraghavan Bringivijayaraghavan, Saurabh Chadha, Abhijit Saurabh, Saravanan Sethuraman, Kenneth L. Wright
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Publication number: 20150331764Abstract: Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The problem is determined to be associated with a primary driver module in the stacked memory device. In response, the primary driver module is disabled and an emergency driver module is enabled. Each of the plurality of slave memory chips are selected using a multiplexing unit to retrieve data using the emergency driver module.Type: ApplicationFiled: May 13, 2014Publication date: November 19, 2015Applicant: International Business Machines CorporationInventors: Saurabh Chadha, Hillery C. Hunter, Kyu-hyoun Kim, Abhijit Saurabh, Saravanan Sethuraman, Kenneth L. Wright
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Publication number: 20150332736Abstract: A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.Type: ApplicationFiled: May 13, 2014Publication date: November 19, 2015Applicant: International Business Machines CorporationInventors: Venkatraghavan Bringivijayaraghavan, Saurabh Chadha, Abhijit Saurabh, Saravanan Sethuraman, Kenneth L. Wright
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Publication number: 20150331768Abstract: Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The problem is determined to be associated with a primary driver module in the stacked memory device. In response, the primary driver module is disabled and an emergency driver module is enabled. Each of the plurality of slave memory chips are selected using a multiplexing unit to retrieve data using the emergency driver module.Type: ApplicationFiled: August 19, 2014Publication date: November 19, 2015Inventors: Saurabh Chadha, Hillery C. Hunter, Kyu-hyoun Kim, Abhijit Saurabh, Saravanan Sethuraman, Kenneth L. Wright
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Publication number: 20150316970Abstract: Methods, apparatuses, and products for budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements (‘ITEs’), each ITE having power utilization information indicating an average power consumption of the ITE, including: determining, by a chassis management module, a total power requirement value based on a sum of the average power consumption for each ITE; increasing, by the chassis management module, the total power requirement value in dependence upon a predetermined power utilization delta; identifying, by the chassis management module, one or more power supplies to provide power to the ITEs in the chassis environment in dependence upon power delivery capabilities of the one or more power supplies and the total power requirement value; and powering on the identified one or more power supplies by the chassis management module.Type: ApplicationFiled: May 5, 2014Publication date: November 5, 2015Applicant: International Business Machines CorporationInventors: SAURABH CHADHA, PRASANNA JAYARAMAN, TONY E. SAWAN