Patents by Inventor Saurabh Dighe

Saurabh Dighe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9317342
    Abstract: A system and method for operating a many-core processor including resilient cores may include determining a frequency variation map for the many-core processor and scheduling execution of a plurality of tasks on respective resilient cores of the many-core processor in accordance to the frequency variation map.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: April 19, 2016
    Assignee: Intel Corporation
    Inventor: Saurabh Dighe
  • Patent number: 9063730
    Abstract: In one embodiment, the present invention includes a processor with multiple cores each having a self-test circuit to determine a frequency profile and a leakage power profile of the corresponding core. In turn, a scheduler is coupled to receive the frequency profiles and the leakage power profiles and to schedule an application on at least some of the cores based on the frequency profiles and the leakage power profiles. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: June 23, 2015
    Assignee: Intel Corporation
    Inventors: Saurabh Dighe, Sriram R. Vangal, Nitin Y. Borkar, Vivek K. De
  • Publication number: 20130318539
    Abstract: A system and method for operating a many-core processor including resilient cores may include determining a frequency variation map for the many-core processor and scheduling execution of a plurality of tasks on respective resilient cores of the many-core processor in accordance to the frequency variation map.
    Type: Application
    Filed: December 23, 2011
    Publication date: November 28, 2013
    Inventor: Saurabh Dighe
  • Publication number: 20120159496
    Abstract: In one embodiment, the present invention includes a processor with multiple cores each having a self-test circuit to determine a frequency profile and a leakage power profile of the corresponding core. In turn, a scheduler is coupled to receive the frequency profiles and the leakage power profiles and to schedule an application on at least some of the cores based on the frequency profiles and the leakage power profiles. Other embodiments are described and claimed.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 21, 2012
    Inventors: Saurabh Dighe, Sriram R. Vangal, Nitin Y. Borkar, Vivek K. De
  • Patent number: 7620119
    Abstract: A communications receiver includes a digital counter to count transitions of a carrier signal subject to on/off keying.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: November 17, 2009
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, Yatin Hoskote, Saurabh Dighe, Nitin Y. Borkar, Vivek K De
  • Publication number: 20050286655
    Abstract: A communications receiver includes a digital counter to count transitions of a carrier signal subject to on/off keying.
    Type: Application
    Filed: June 29, 2004
    Publication date: December 29, 2005
    Inventors: Siva Narendra, Yatin Hoskote, Saurabh Dighe, Nitin Borkar, Vivek De