Patents by Inventor Saurabh Dutta Chowdhury

Saurabh Dutta Chowdhury has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7915175
    Abstract: A method of forming a semiconductor structure comprises etching an anti-reflective coating on a substrate with a first plasma comprising bromine and oxygen; and etching a nitride layer on the substrate with a second plasma comprising bromine and oxygen.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: March 29, 2011
    Assignee: Cypress Semiconductor Corporation
    Inventors: Saurabh Dutta Chowdhury, Helena Stadniychuk
  • Patent number: 7229929
    Abstract: A method of making a semiconductor structure, comprises etching a nitride layer with a plasma to form a patterned nitride layer. The nitride layer is on a semiconductor substrate, a photoresist layer is on the nitride layer, and the plasma is prepared from a gas mixture comprising CF4 and CHF3 at a pressure of at least 10 mTorr.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: June 12, 2007
    Assignee: Cypress Semiconductor Corporation
    Inventor: Saurabh Dutta Chowdhury
  • Patent number: 7078334
    Abstract: According to one embodiment, a method (100) may include forming a first insulating layer over a semiconductor substrate (step 102), forming a hard mask layer (step 104), and forming a photoresist etch mask having a thickness of less than about 4,000 angstroms (step 106). Such a reduced thickness may conventionally lead to uncontrolled etching and/or may require multiple steps to ensure feature formation. A method (100) may further include etching an opening through at least one half the thickness of the hard mask layer to form a hard mask (step 108) and etching through a first insulating layer without first removing a photoresist layer (step 110). Such etching can essentially consume a photoresist layer, however controllability can be maintained as etching may continue with a hard mask in place.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: July 18, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventors: Saurabh Dutta Chowdhury, Mehran Sedigh, Chan Lon Yang, Prabhu Goplana
  • Publication number: 20040110387
    Abstract: A method of making a semiconductor structure, comprises etching a nitride layer with a plasma to form a patterned nitride layer. The nitride layer is on a semiconductor substrate, a photoresist layer is on the nitride layer, and the plasma is prepared from a gas mixture comprising CF4 and CHF3 at a pressure of at least 10 mtorr.
    Type: Application
    Filed: December 6, 2002
    Publication date: June 10, 2004
    Inventor: Saurabh Dutta Chowdhury
  • Patent number: 6713831
    Abstract: A method and a system are provided for forming a borderless contact structure. In particular, a method is provided which includes using an inorganic anti-reflective coating layer as an etch stop to form a borderless contact structure. In some embodiments, the method may include patterning an interconnect line above an inorganic layer with anti-reflective properties and depositing an upper interlevel dielectric layer above the interconnect line. A trench may then be etched within the upper interlevel dielectric layer such that a borderless contact structure may be formed in contact with said interconnect line. Consequently, a semiconductor topography is provided, in such an embodiment, which includes an inorganic anti-reflective coating layer arranged below an interconnect line and a contact structure arranged upon the interconnect line. In some embodiments, a width of the contact structure may be greater than a width of the interconnect line.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: March 30, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Sharmin Sadoughi, Mira Ben-Tzur, Michal E. Fastow, Saurabh Dutta Chowdhury
  • Patent number: 6620715
    Abstract: A method is provided for fabricating a device, which includes device components and spacings that may each have a final dimension that is smaller than a minimum dimension obtainable by a photolithography process used to form the device components. In particular, the method may include patterning an upper layer of the semiconductor topography using the photolithography process to form a device mask having dimensions substantially equal to or greater than the minimum dimension. The method may further include trimming the device mask and forming a semiconductor structure in alignment with the trimmed device mask. In addition, the method may include patterning the semiconductor structure to form device components and spacings therebetween. In general, patterning the semiconductor structure may include tapering a first layer of the semiconductor structure and removing an exposed portion of a second layer of the semiconductor structure.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: September 16, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventors: Alain P. Blosse, Saurabh Dutta Chowdhury