Patents by Inventor Saurabh Garg

Saurabh Garg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200210224
    Abstract: Methods and apparatus for acknowledging and verifying the completion of data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a host-side processor delivers payloads over the IPC link using one or more transfer descriptors (TDs) that describe the payloads. The TDs are written in a particular order to a transfer descriptor ring (TR) in a shared memory between the host and peripheral processors. The peripheral reads the TDs over the IPC link and transacts, in proper order, the data retrieved based on the TDs. To acknowledge the transaction, the peripheral processor writes completion descriptors (CDs) to a completion descriptor ring (CR). The CD may complete one or more TDs; in optimized completion schemes the CD completes all outstanding TDs up to and including the expressly completed TD.
    Type: Application
    Filed: March 9, 2020
    Publication date: July 2, 2020
    Inventors: Karan Sanghi, Saurabh Garg, Vladislav V. Petkov
  • Patent number: 10684670
    Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: June 16, 2020
    Assignee: Apple Inc.
    Inventors: Karan Sanghi, Saurabh Garg, Haining Zhang
  • Publication number: 20200177672
    Abstract: A control device configuration system may receive, store, process, and/or display control device configuration information. The control device configuration system may filter the control device configuration information based on user selections of configuration options for configuration parameters. The control device configuration system may identify compatible and incompatible configuration options for various configuration parameters. The control device configuration system may allow selections of the incompatible configuration options. The control device configuration system may adjust how it filters the control device configuration information based on the selections of the incompatible configuration options. The control device configuration system may implement a configuration model that includes configuration parameter groups for efficient evaluation of user selections.
    Type: Application
    Filed: September 30, 2019
    Publication date: June 4, 2020
    Applicant: Lutron Technology Company LLC
    Inventors: Ram Kripal Prasad, Saurabh Garg
  • Publication number: 20200174953
    Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.
    Type: Application
    Filed: February 3, 2020
    Publication date: June 4, 2020
    Inventors: Karan Sanghi, Vladislav Petkov, Radha Kumar Pulyala, Saurabh Garg, Haining Zhang
  • Publication number: 20200104195
    Abstract: Methods and apparatus for correcting out-of-order data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a peripheral-side processor receives data from an external device and stores it to memory. The host processor writes data structures (transfer descriptors) describing the received data, regardless of the order the data was received from the external device. The transfer descriptors are written to a memory structure (transfer descriptor ring) in memory shared between the host and peripheral processors. The peripheral reads the transfer descriptors and writes data structures (completion descriptors) to another memory structure (completion descriptor ring). The completion descriptors are written to enable the host processor to retrieve the stored data in the correct order. In optimized variants, a completion descriptor describes groups of transfer descriptors.
    Type: Application
    Filed: November 2, 2018
    Publication date: April 2, 2020
    Inventors: KARAN SANGHI, Saurabh Garg
  • Publication number: 20200103932
    Abstract: Methods and apparatus for synchronization of time between independently operable processors. Time synchronization between independently operable processors is complicated by a variety of factors. For example, neither independently operable processor controls the other processor's task scheduling, power, or clocking. In one exemplary embodiment, a processor can initiates a time synchronization process by disabling power state machines and transacting timestamps for a commonly observed event. In one such embodiment, timestamps may be transferred via inter-processor communication (IPC) mechanisms (e.g., transfer descriptors (TDs), and completion descriptors (CDs)). Both processors may thereafter coordinate in time synchronization efforts (e.g., speeding up or slowing down their respective clocks, etc.).
    Type: Application
    Filed: November 2, 2018
    Publication date: April 2, 2020
    Inventors: Karan Sanghi, Saurabh Garg
  • Publication number: 20200097595
    Abstract: Certain embodiments involve augmenting project data with searchable metadata for facilitating project queries. A method includes receiving metadata of the set of projects and identifying a filter within the metadata. The method also includes generating a first vector representing a first project of the set of projects and generating a second vector representing a second project of the set of projects. Further, the method includes grouping the first vector and the second vector into a project cluster based on the first vector and the second vector being within a threshold distance. The project cluster represents a set of filters associated with a subset of projects. Additionally, the method includes assigning a searchable tag to the project cluster based on the filter being a majority filter of the project cluster. The searchable tag includes metadata that facilitates locating the projects responsive to a query to the set of projects.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Saurabh Garg, Shubhi Rastogi, Shiladitya Bose, Hyder Ziaee, Hina Watts
  • Patent number: 10591976
    Abstract: Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: March 17, 2020
    Assignee: Apple Inc.
    Inventors: Saurabh Garg, Karan Sanghi, Vladislav Petkov, Richard Solotke
  • Patent number: 10585699
    Abstract: Methods and apparatus for acknowledging and verifying the completion of data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a host-side processor delivers payloads over the IPC link using one or more transfer descriptors (TDs) that describe the payloads. The TDs are written in a particular order to a transfer descriptor ring (TR) in a shared memory between the host and peripheral processors. The peripheral reads the TDs over the IPC link and transacts, in proper order, the data retrieved based on the TDs. To acknowledge the transaction, the peripheral processor writes completion descriptors (CDs) to a completion descriptor ring (CR). The CD may complete one or more TDs; in optimized completion schemes the CD completes all outstanding TDs up to and including the expressly completed TD.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: March 10, 2020
    Assignee: Apple Inc.
    Inventors: Karan Sanghi, Saurabh Garg, Vladislav V. Petkov
  • Publication number: 20200065244
    Abstract: Methods and apparatus for using and controlling a jointly shared memory-mapped region between multiple processors in a pass-through manner. Existing data pipe input/output (I/O) techniques for mobile device operation enable high speed data transfers, decoupled independent operation of processors, reduced software complexity, reduced power consumption, etc. However, legacy functions and capabilities may only receive marginal benefits from data pipe I/O operation, and in some cases, may even suffer adverse effects from e.g., processing overhead and/or context switching. The present disclosure is directed to dynamically isolating and reaping back a jointly shared memory space for data transfer in a “pass through” manner which does not require kernel space intervention. More directly, a jointly shared region of host memory is accessible to both the peripheral client and the host client in user space.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 27, 2020
    Inventors: Karan Sanghi, Saurabh Garg, Jason McElrath
  • Publication number: 20200065161
    Abstract: Methods and apparatus for transacting multiple data flows between multiple processors. In one such implementation, multiple data pipes are aggregated over a common transfer data structure. Completion status information corresponding to each data pipe is provided over individual completion data structures. Allocating a common fixed pool of resources for data transfer can be used in a variety of different load balancing and/or prioritization schemes; however, individualized completion status allows for individualized data pipe reclamation. Unlike prior art solutions which dynamically created and pre-allocated memory space for each data pipe individually, the disclosed embodiments can only request resources from a fixed pool. In other words, outstanding requests are queued (rather than immediately serviced with a new memory allocation), thus overall bandwidth remains constrained regardless of the number of data pipes that are opened and/or closed.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 27, 2020
    Inventors: Karan Sanghi, Saurabh Garg
  • Patent number: 10572390
    Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: February 25, 2020
    Assignee: Apple Inc.
    Inventors: Vladislav Petkov, Haining Zhang, Karan Sanghi, Saurabh Garg
  • Patent number: 10558580
    Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: February 11, 2020
    Assignee: Apple Inc.
    Inventors: Vladislav Petkov, Haining Zhang, Karan Sanghi, Saurabh Garg
  • Patent number: 10551906
    Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: February 4, 2020
    Assignee: Apple Inc.
    Inventors: Karan Sanghi, Saurabh Garg, Haining Zhang
  • Patent number: 10551902
    Abstract: Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: February 4, 2020
    Assignee: Apple Inc.
    Inventors: Saurabh Garg, Karan Sanghi, Vladislav Petkov, Richard Solotke
  • Patent number: 10552352
    Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: February 4, 2020
    Assignee: Apple Inc.
    Inventors: Karan Sanghi, Vladislav Petkov, Radha Kumar Pulyala, Saurabh Garg, Haining Zhang
  • Patent number: 10551328
    Abstract: A test fixture includes an outer conductor and an inner conductor disposed within and electrically isolated from the outer conductor. The inner conductor includes a top portion having a first diameter, a bottom portion having a second diameter, and a third portion proximate the bottom portion that has a third diameter that is less than the second diameter and is greater than the first diameter. An electrical property of a chamber component disposed within the outer conductor is measurable based on application of a signal to at least one of the outer conductor or the inner conductor.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: February 4, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Satoru Kobayashi, Yufei Zhu, Saurabh Garg, Soonam Park, Dmitry Lubomirsky
  • Publication number: 20200034186
    Abstract: Methods and apparatus for acknowledging and verifying the completion of data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a host-side processor delivers payloads over the IPC link using one or more transfer descriptors (TDs) that describe the payloads. The TDs are written in a particular order to a transfer descriptor ring (TR) in a shared memory between the host and peripheral processors. The peripheral reads the TDs over the IPC link and transacts, in proper order, the data retrieved based on the TDs. To acknowledge the transaction, the peripheral processor writes completion descriptors (CDs) to a completion descriptor ring (CR). The CD may complete one or more TDs; in optimized completion schemes the CD completes all outstanding TDs up to and including the expressly completed TD.
    Type: Application
    Filed: July 30, 2018
    Publication date: January 30, 2020
    Inventors: KARAN SANGHI, Saurabh Garg, Vladislav V. Petkov
  • Publication number: 20200026668
    Abstract: Methods and apparatus for reducing bus overhead with virtualized transfer rings. The Inter-Processor Communications (IPC) bus uses a ring buffer (e.g., a so-called Transfer Ring (TR)) to provide Direct Memory Access (DMA)-like memory access between processors. However, performing small transactions within the TR inefficiently uses bus overhead. A Virtualized Transfer Ring (VTR) is a null data structure that doesn't require any backing memory allocation. A processor servicing a VTR data transfer includes the data payload as part of an optional header/footer data structure within a completion ring (CR).
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Karan Sanghi, Saurabh Garg, Vladislav V. Petkov
  • Publication number: 20190385823
    Abstract: Gas distribution assemblies are described including an annular body, an upper plate, and a lower plate. The upper plate may define a first plurality of apertures, and the lower plate may define a second and third plurality of apertures. The upper and lower plates may be coupled with one another and the annular body such that the first and second apertures produce channels through the gas distribution assemblies, and a volume is defined between the upper and lower plates.
    Type: Application
    Filed: July 15, 2019
    Publication date: December 19, 2019
    Applicant: Applied Materials, Inc.
    Inventors: Qiwei Liang, Xinglong Chen, Kien Chuc, Dmitry Lubomirsky, Soonam Park, Jang-Gyoo Yang, Shankar Venkataraman, Toan Tran, Kimberly Hinckley, Saurabh Garg