Abstract: Various embodiments of the present disclosure provide computer forecasting techniques for initiating presentation of an interactive user interface. The techniques may include receiving one or more candidate prediction-based actions and generating a plurality of causal risk-based impact scores with respect to a candidate prediction-based action. The techniques include generating a plurality of causal quality-based impact scores and an action sequence for a plurality of evaluation entities and generating a causal net impact score based on (i) an aggregation of the plurality of causal risk-based impact scores and the plurality of causal quality-based impact scores and (ii) a sequence impact metric corresponding to the action sequence. The techniques include generating a sequence ranking for the action sequence and initiating a presentation of an interactive user interface reflective of the action sequence and the sequence ranking.

Abstract: Various embodiments of the present disclosure provide computer forecasting techniques for forecasting holistic, causal risk-based scores. The techniques may include generating a predictive risk-based opportunity score for an evaluation entity based on (i) a plurality of engagement scores and (ii) a plurality of predictive risk scores respectively corresponding to a plurality of predictive entities within an entity cohort associated with the evaluation entity. Using action-specific causal inference models, a predictive impact score of a prediction-based action on the evaluation entity is generated and used to generate a causal gap closure score for the evaluation entity based on a gap closure rate associated with the evaluation entity. The techniques include generating a causal risk-based impact score for the prediction-based action and the evaluation entity based on the predictive risk-based opportunity score, the predictive impact score, and a predictive improvement measure.

Abstract: Various embodiments of the present disclosure provide computer forecasting techniques for forecasting holistic, categorical improvement predictions. The techniques may include generating a predictive quality performance measure based on (i) an evaluation entity of a plurality of evaluation entities within an entity group and (ii) a quality metric of a plurality of quality metrics corresponding to a categorical ranking scheme for the entity group. The techniques include using an action-specific causal inference model to generate a metric-specific predictive impact measure. The techniques include generating a metric-level categorical improvement prediction and a categorical improvement prediction for the entity group with respect to the categorical ranking scheme based on a weighted aggregation of the metric-level categorical improvement prediction and a plurality of metric-level categorical improvement predictions respectively corresponding the plurality of quality metrics.

Abstract: A multi-cavity package includes a single metal flange having first and second opposing main surfaces. The multi-cavity package also includes a dielectric material attached to the first main surface of the single metal flange. The dielectric material includes a first surface facing the single metal flange, and a second surface facing away from the first surface. The dielectric material also includes a plurality of openings exposing different regions of the first main surface of the single metal flange. The dielectric material also includes a lateral extension that overhangs the single metal flange. A corresponding method of manufacturing is also provided.

Abstract: A multi-cavity package includes a single metal flange having first and second opposing main surfaces. The multi-cavity package also includes a circuit board attached to the first main surface of the single metal flange. The circuit board includes a first surface facing the single metal flange, and a second surface facing away from the first surface. The circuit board also includes a plurality of openings exposing different regions of the first main surface of the single metal flange. The circuit board also includes a lateral extension that overhangs the single metal flange. A corresponding method of manufacturing is also provided.

Abstract: A multi-cavity package includes a single metal flange having first and second opposing main surfaces. The multi-cavity package also includes a circuit board attached to the first main surface of the single metal flange. The circuit board includes a first surface facing the single metal flange, and a second surface facing away from the first surface. The circuit board also includes a plurality of openings exposing different regions of the first main surface of the single metal flange. The circuit board also includes a lateral extension that overhangs the single metal flange. A corresponding method of manufacturing is also provided.

Abstract: A multi-cavity package includes a single metal flange having first and second opposing main surfaces, a circuit board attached to the first main surface of the single metal flange, the circuit board having a plurality of openings which expose different regions of the first main surface of the single metal flange, and a plurality of semiconductor dies each of which is disposed in one of the openings in the circuit board and attached to the first main surface of the single metal flange. The circuit board includes a plurality of metal traces for electrically interconnecting the semiconductor dies to form a circuit. A corresponding method of manufacturing is also provided.

Abstract: Exemplary embodiments including an amplifier circuit that includes a radio-frequency (RF) amplifier comprising an input terminal and an output terminal, the RF amplifier being configured to amplify, across a wideband frequency range, an RF signal applied to the input terminal to generate an amplified RF signal at the output terminal. The amplifier circuit also includes a first impedance matching network connected to the RF amplifier output terminal. The first impedance matching network includes a first reactive circuit, having substantially fixed impedance, connected between the RF amplifier input terminal and ground; a second reactive circuit; and a switching device configured to couple the second reactive circuit to the first reactive circuit in an ON state, and to decouple the second reactive circuit from the first reactive circuit in an OFF state. In some embodiments, the amplifier circuit can include a second impedance matching network connected to the RF amplifier input terminal.

Abstract: Exemplary embodiments including an amplifier circuit that includes a radio-frequency (RF) amplifier comprising an input terminal and an output terminal, the RF amplifier being configured to amplify, across a wideband frequency range, an RF signal applied to the input terminal to generate an amplified RF signal at the output terminal. The amplifier circuit also includes a first impedance matching network connected to the RF amplifier output terminal. The first impedance matching network includes a first reactive circuit, having substantially fixed impedance, connected between the RF amplifier input terminal and ground; a second reactive circuit; and a switching device configured to couple the second reactive circuit to the first reactive circuit in an ON state, and to decouple the second reactive circuit from the first reactive circuit in an OFF state. In some embodiments, the amplifier circuit can include a second impedance matching network connected to the RF amplifier input terminal.

Abstract: An amplifier is configured to amplify an RF signal as between an input terminal and an output terminal across a wideband frequency range. A first LC network is connected to the input terminal and has first and second reactive components. A first switching device is connected between the first and second reactive components and couples both the first and second reactive components to the input terminal in an ON state, and disconnects the second reactive component from the input terminal in an OFF state. A second LC network is connected to the output terminal and has third and fourth reactive components. A second switching device is connected between the third and fourth reactive components and couples both the third and fourth reactive components to the output terminal in an ON state and disconnects the fourth reactive component from the output terminal in an OFF state.

Abstract: Methods and apparatus for optimizing resource utilization in distributed storage systems. A data migration technique is described that may operate in the background in a distributed storage data center to migrate data among a fleet of storage units to achieve a substantially even and randomized data storage distribution among all storage units in the fleet. When new storage units are added to the fleet and coupled to the data center network, the new storage units are detected. Instead of processing and storing new data to the newly added storage units, as in conventional distributed storage systems, the new units are blocked from general client I/O to allow the data migration technique to migrate data from other, previously installed storage hardware in the data center onto the new storage hardware. Once the storage load on the new storage units is balanced with the rest of the fleet, the new storage units are released for general client I/O.

Abstract: An amplifier is configured to amplify an RF signal as between an input terminal and an output terminal across a wideband frequency range. A first LC network is connected to the input terminal and has first and second reactive components. A first switching device is connected between the first and second reactive components and couples both the first and second reactive components to the input terminal in an ON state, and disconnects the second reactive component from the input terminal in an OFF state. A second LC network is connected to the output terminal and has third and fourth reactive components. A second switching device is connected between the third and fourth reactive components and couples both the third and fourth reactive components to the output terminal in an ON state and disconnects the fourth reactive component from the output terminal in in an OFF state.

Abstract: A multi-cavity package includes a single metal flange having first and second opposing main surfaces, a circuit board attached to the first main surface of the single metal flange, the circuit board having a plurality of openings which expose different regions of the first main surface of the single metal flange, and a plurality of semiconductor dies each of which is disposed in one of the openings in the circuit board and attached to the first main surface of the single metal flange. The circuit board includes a plurality of metal traces for electrically interconnecting the semiconductor dies to form a circuit. A corresponding method of manufacturing is also provided.

Abstract: Methods and apparatus for optimizing resource utilization in distributed storage systems. A data migration technique is described that may operate in the background in a distributed storage data center to migrate data among a fleet of storage units to achieve a substantially even and randomized data storage distribution among all storage units in the fleet. When new storage units are added to the fleet and coupled to the data center network, the new storage units are detected. Instead of processing and storing new data to the newly added storage units, as in conventional distributed storage systems, the new units are blocked from general client I/O to allow the data migration technique to migrate data from other, previously installed storage hardware in the data center onto the new storage hardware. Once the storage load on the new storage units is balanced with the rest of the fleet, the new storage units are released for general client I/O.

Abstract: A power transistor die includes a transistor formed in a semiconductor body. The transistor has a gate terminal, an output terminal and a third terminal. The gate terminal controls a conduction channel between the output terminal and the third terminal. The power transistor die further includes a structured first metal layer disposed on and insulated from the semiconductor body. The structured first metal layer is connected to the output terminal of the transistor. The power transistor die also includes a first bond pad disposed on and insulated from the semiconductor body. The first bond pad forms an output terminal of the power transistor die and is capacitively coupled to the structured first metal layer so as to form a series capacitance between the output terminal of the transistor and the first bond pad. A power semiconductor package including the power transistor die is also provided.

Abstract: Methods and apparatus for optimizing resource utilization in distributed storage systems. A data migration technique is described that may operate in the background in a distributed storage data center to migrate data among a fleet of storage units to achieve a substantially even and randomized data storage distribution among all storage units in the fleet. When new storage units are added to the fleet and coupled to the data center network, the new storage units are detected. Instead of processing and storing new data to the newly added storage units, as in conventional distributed storage systems, the new units are blocked from general client I/O to allow the data migration technique to migrate data from other, previously installed storage hardware in the data center onto the new storage hardware. Once the storage load on the new storage units is balanced with the rest of the fleet, the new storage units are released for general client I/O.

Abstract: A power circuit includes a RF transistor and an input match network coupled to an input to the RF transistor and to an input to the power circuit. The input match network includes a resistor, an inductor and a first capacitor coupled together in series between the input to the RF transistor and a ground, and a second capacitor coupled in parallel with at least the resistor. The value of the second capacitor is selected so that the resistor is bypassed over at least a portion of the high frequency range of the power circuit.

Abstract: A power circuit includes a RF transistor and an input match network coupled to an input to the RF transistor and to an input to the power circuit. The input match network includes a resistor, an inductor and a first capacitor coupled together in series between the input to the RF transistor and a ground, and a second capacitor coupled in parallel with at least the resistor. The value of the second capacitor is selected so that the resistor is bypassed over at least a portion of the high frequency range of the power circuit.

Abstract: A symmetric Doherty amplifier includes a main amplifier and a peaking amplifier of the same size as the main amplifier. The symmetric Doherty amplifier is configured to operate at peak output power when the main amplifier and the peaking amplifier are each in saturation, and at output-back-off (OBO) when the main amplifier is in saturation and the peaking amplifier is not in saturation. Phase shift circuitry is configured to shift the phase at an output of the peaking amplifier at OBO so that a load impedance seen by the main amplifier and efficiency of the symmetric Doherty amplifier both increase at OBO as a function of the phase shift at the peaking amplifier output.

Abstract: A power circuit includes a RF transistor and an input match network coupled to an input to the RF transistor and to an input to the power circuit. The input match network includes a resistor, an inductor and a capacitor that are coupled together in series between the input to the RF transistor and a ground. The values of the resistor and the inductor are selected to match an input impedance of the RF transistor to a source impedance at the input to the power circuit over at least a portion of a high frequency range, wherein the value of the capacitor has a substantially negligible contribution to the match at the high frequency range. The value of the capacitor is selected so that the series combination of the resistor, the inductor and the capacitor substantially reduce the magnitude of the impedance presented to the input of the RF transistor in a low frequency range relative to the source impedance at the input to the power circuit.