Patents by Inventor Saurabh Goyal

Saurabh Goyal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240213978
    Abstract: A bootstrap switch circuit includes a transistor-based switch controlled by a first gate signal and a leakage protection transistor controlled by a second gate signal configured to reduce gate induced drain leakage in the transistor-based switch A first gate driver is included that produces a first gate signal at its output so that the first gate signal turns on the transistor-based switch during a sampling mode and turns off the transistor-based switch during a hold mode. A second gate driver is included that produces a second gate signal at its output and to receive the output signal of the bootstrap switch circuit so that the second gate signal turns on the leakage protection transistor during the sampling mode and turns off the leakage protection transistor during the hold mode and the second gate signal is based upon the output signal of the bootstrap switch circuit.
    Type: Application
    Filed: March 8, 2023
    Publication date: June 27, 2024
    Inventors: Saurabh Goyal, Krishna Thakur
  • Publication number: 20240204757
    Abstract: An integrated circuit including a functional circuit, a tuning circuit, and a control circuit is provided. The functional and control circuits generate an output signal and a digital code, respectively. The tuning circuit tunes the functional circuit based on the digital code to control an attribute of the output signal. The digital code is iteratively adjusted such that the attribute of the output signal is maintained within a predefined range. When the digital code corresponds to a cliff value, the digital code for a subsequent iteration is adjusted by a non-unit offset value such that a difference between the attribute for the cliff value and for the subsequent digital code is within a tolerance limit. The digital code is indicative of coarse and fine parameters, and for each value of the coarse parameter, the cliff value corresponds to the lowest or highest value of the fine parameter.
    Type: Application
    Filed: June 9, 2023
    Publication date: June 20, 2024
    Inventors: Saurabh Goyal, Divya Tripathi, Krishna Thakur, Deependra Kumar Jain
  • Publication number: 20240178858
    Abstract: A low current, adaptively-biased switched resistor digital-to-analog converter (RDAC) circuit, method and apparatus are provided with a coarse trim ladder and a fine trim ladder connected with a plurality of NFET switches to generate an output reference voltage from an input supply voltage, where the bulk semiconductor substrate regions for the NFET switches in at least the fine trim ladder are driven by a unity gain buffer which is connected in feedback to receive the output reference voltage and to generate a buffered reference voltage which is directly connected to bulk semiconductor regions of the NFET switches, thereby providing a low current, low circuit area solution with reduced leakage current and temperature variation.
    Type: Application
    Filed: May 11, 2023
    Publication date: May 30, 2024
    Inventors: Saurabh Goyal, Krishna Thakur, Divya Tripathi, Deependra Kumar Jain
  • Publication number: 20240161915
    Abstract: A patient access determination system configured to extract health related data from a data source to form extracted health data, generate a plurality of data pipelines for conveying the extracted health data, and store the extracted health data conveyed over one or more of the data pipelines in a data model to form stored health data. The data model includes tables for organizing and storing the extracted health data. The system also determines from at least the patient encounter data forming part of the stored health data a number of lost appointments that can be recovered by the healthcare facility and apply one or more machine learning models to the stored health data to generate predictions therefrom. The system can also generate one or more user interfaces for displaying selected portions of the stored health data and the predictions.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 16, 2024
    Inventors: Eduardo Lopez MOTA, Alex OBENAUF, Michael E. FECTEAU, Saurabh GOYAL
  • Patent number: 11927493
    Abstract: A temperature sensor includes a sensing element and a load. Multiple different currents pass through the sensing element in a sequential manner. Based on each current that passes through the sensing element, the sensing element outputs a complementary-to-absolute-temperature (CTAT) voltage and another current. Further, the currents that pass through the sensing element and the currents that the sensing element output separately pass through the load and result in the generation of multiple load voltages across the load. A current density ratio of the temperature sensor is determined based on the load voltages generated across the load. Further, a temperature value indicative of a temperature sensed by the temperature sensor is generated based on the current density ratio and the CTAT voltages outputted by the sensing element based on the different currents that pass therethrough.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: March 12, 2024
    Assignee: NXP B.V.
    Inventors: Saurabh Goyal, Sanjay Kumar Wadhwa, Firas N. Abughazaleh, Atul Kumar
  • Publication number: 20240012720
    Abstract: A data management and storage (DMS) cluster of peer DMS nodes manages migration of an application between a primary compute infrastructure and a secondary compute infrastructure. The secondary compute infrastructure may be a failover environment for the primary compute infrastructure. Primary snapshots of virtual machines of the application in the primary compute infrastructure are generated, and provided to the secondary compute infrastructure. During a failover, the primary snapshots are deployed in the secondary compute infrastructure as virtual machines. Secondary snapshots of the virtual machines are generated, where the secondary snapshots are incremental snapshots of the primary snapshots. In failback, the secondary snapshots are provided to the primary compute infrastructure, where they are combined with the primary snapshots into construct a current state of the application, and the application is deployed in the current state by deploying virtual machines on the primary compute infrastructure.
    Type: Application
    Filed: September 19, 2023
    Publication date: January 11, 2024
    Inventors: Zhicong Wang, Benjamin Meadowcroft, Biswaroop Palit, Atanu Chakraborty, Hardik Vohra, Abhay Mitra, Saurabh Goyal, Sanjari Srivastava, Swapnil Agarwal, Rahil Shah, Mudit Malpani, Janmejay Singh, Ajay Arvind Bhave, Prateek Pandey
  • Publication number: 20230419710
    Abstract: A method, computer system, and a computer program product for information extraction is provided. The present invention may include receiving, by a handwriting detection model of an integrated system, a mixed-text document including a combination of typed text and handwritten text, where the received mixed-text document includes at least one key-value pair. The present invention may also include receiving, by the handwriting detection model of the integrated system, a first location information of at least one key from the at least one key-value pair in the received mixed-text document. The present invention may further include detecting, by the handwriting detection model of the integrated system, at least one handwritten text in the received mixed-text document based on the received first location information of the at least one key.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 28, 2023
    Inventors: Saurabh Goyal, Catherine Finegan-Dollak, ASHISH VERMA
  • Publication number: 20230361772
    Abstract: An integrated circuit (IC) includes one or more active transistors and multiple series-coupled dummy transistors. The dummy transistors are coupled between two active transistors and/or at the ends of each active transistor. When the dummy transistors are coupled between two active transistors, apart from two conductive regions that are coupled to two active transistors, each remaining conductive region of the dummy transistors is maintained in a floating state to control a leakage current between the two active transistors. Similarly, when the dummy transistors are coupled at an end of one active transistor, apart from one conductive region that is coupled to the active transistor, each remaining conductive region of the dummy transistors is maintained in the floating state to control a leakage current between the active transistor and the dummy transistors.
    Type: Application
    Filed: May 5, 2022
    Publication date: November 9, 2023
    Inventors: Sanjay Kumar Wadhwa, Divya Tripathi, Saurabh Goyal, Alvin Leng Sun Loke, Manish Kumar Upadhyay
  • Patent number: 11797395
    Abstract: A data management and storage (DMS) cluster of peer DMS nodes manages migration of an application between a primary compute infrastructure and a secondary compute infrastructure. The secondary compute infrastructure may be a failover environment for the primary compute infrastructure. Primary snapshots of virtual machines of the application in the primary compute infrastructure are generated, and provided to the secondary compute infrastructure. During a failover, the primary snapshots are deployed in the secondary compute infrastructure as virtual machines. Secondary snapshots of the virtual machines are generated, where the secondary snapshots are incremental snapshots of the primary snapshots. In failback, the secondary snapshots are provided to the primary compute infrastructure, where they are combined with the primary snapshots into construct a current state of the application, and the application is deployed in the current state by deploying virtual machines on the primary compute infrastructure.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: October 24, 2023
    Assignee: Rubrik, Inc.
    Inventors: Zhicong Wang, Benjamin Meadowcroft, Biswaroop Palit, Atanu Chakraborty, Hardik Vohra, Abhay Mitra, Saurabh Goyal, Sanjari Srivastava, Swapnil Agarwal, Rahil Shah, Mudit Malpani, Janmejay Singh, Ajay Arvind Bhave, Prateek Pandey
  • Patent number: 11763082
    Abstract: Methods, systems, and computer program products for accelerating inference of transformer-based models are provided herein. A computer-implemented method includes obtaining a machine learning model comprising a plurality of transformer blocks, a task, and a natural language dataset; generating a compressed version of the machine learning model based on the task and the natural language dataset, wherein the generating comprises: obtaining at least one set of tokens, wherein each token in the set corresponds to one of the items in the natural language dataset, identifying and removing one or more redundant output activations of different ones of the plurality of transformer blocks for the at least one set of tokens, and adding one or more input activations corresponding to the one or more removed output activations into the machine learning model at subsequent ones of the plurality of the transformer blocks; and outputting the compressed version of the machine learning model to at least one user.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: September 19, 2023
    Assignee: International Business Machines Corporation
    Inventors: Saurabh Goyal, Anamitra Roy Choudhury, Saurabh Manish Raje, Venkatesan T. Chakaravarthy, Yogish Sabharwal, Ashish Verma
  • Publication number: 20230184594
    Abstract: A temperature sensor includes a sensing element and a load. Multiple different currents pass through the sensing element in a sequential manner. Based on each current that passes through the sensing element, the sensing element outputs a complementary-to-absolute-temperature (CTAT) voltage and another current. Further, the currents that pass through the sensing element and the currents that the sensing element output separately pass through the load and result in the generation of multiple load voltages across the load. A current density ratio of the temperature sensor is determined based on the load voltages generated across the load. Further, a temperature value indicative of a temperature sensed by the temperature sensor is generated based on the current density ratio and the CTAT voltages outputted by the sensing element based on the different currents that pass therethrough.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 15, 2023
    Inventors: Saurabh Goyal, Sanjay Kumar Wadhwa, Firas N. Abughazaleh, Atul Kumar
  • Patent number: 11669409
    Abstract: A data management and storage (DMS) cluster of peer DMS nodes manages migration of an application between a primary compute infrastructure and a secondary compute infrastructure. The secondary compute infrastructure may be a failover environment for the primary compute infrastructure. Primary snapshots of virtual machines of the application in the primary compute infrastructure are generated, and provided to the secondary compute infrastructure. During a failover, the primary snapshots are deployed in the secondary compute infrastructure as virtual machines. Secondary snapshots of the virtual machines are generated, where the secondary snapshots are incremental snapshots of the primary snapshots. In failback, the secondary snapshots are provided to the primary compute infrastructure, where they are combined with the primary snapshots into construct a current state of the application, and the application is deployed in the current state by deploying virtual machines on the primary compute infrastructure.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: June 6, 2023
    Assignee: Rubrik, Inc.
    Inventors: Zhicong Wang, Benjamin Meadowcroft, Biswaroop Palit, Atanu Chakraborty, Hardik Vohra, Abhay Mitra, Saurabh Goyal, Sanjari Srivastava, Swapnil Agarwal, Rahil Shah, Mudit Malpani, Janmejay Singh, Ajay Arvind Bhave, Prateek Pandey
  • Patent number: 11663085
    Abstract: A data management and storage (DMS) cluster of peer DMS nodes manages data of an application distributed across a set of machines of a compute infrastructure. A DMS node associates a set of machines with the application, and generates data fetch jobs for the set of machines for execution by multiple peer DMS nodes. The DMS node determining whether each of the data fetch jobs for the set of machines is ready for execution by the peer DMS nodes. In response to determining that each of the data fetch jobs is ready for execution, the peer DMS nodes execute the data fetch jobs to generate snapshots of the set of machines. The snapshots may be full or incremental snapshots, and collectively form a snapshot of the application.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: May 30, 2023
    Assignee: Rubrik, Inc.
    Inventors: Zhicong Wang, Benjamin Meadowcroft, Biswaroop Palit, Atanu Chakraborty, Hardik Vohra, Abhay Mitra, Saurabh Goyal, Sanjari Srivastava, Swapnil Agarwal, Rahil Shah, Mudit Malpani, Janmejay Singh, Ajay Arvind Bhave, Prateek Pandey
  • Publication number: 20230153210
    Abstract: A data management and storage (DMS) cluster of peer DMS nodes manages migration of an application between a primary compute infrastructure and a secondary compute infrastructure. The secondary compute infrastructure may be a failover environment for the primary compute infrastructure. Primary snapshots of virtual machines of the application in the primary compute infrastructure are generated, and provided to the secondary compute infrastructure. During a failover, the primary snapshots are deployed in the secondary compute infrastructure as virtual machines. Secondary snapshots of the virtual machines are generated, where the secondary snapshots are incremental snapshots of the primary snapshots. In failback, the secondary snapshots are provided to the primary compute infrastructure, where they are combined with the primary snapshots into construct a current state of the application, and the application is deployed in the current state by deploying virtual machines on the primary compute infrastructure.
    Type: Application
    Filed: January 13, 2023
    Publication date: May 18, 2023
    Inventors: Zhicong Wang, Benjamin Meadowcroft, Biswaroop Palit, Atanu Chakraborty, Hardik Vohra, Abhay Mitra, Saurabh Goyal, Sanjari Srivastava, Swapnil Agarwal, Rahil Shah, Mudit Malpani, Janmejay Singh, Ajay Arvind Bhave, Prateek Pandey
  • Patent number: 11586932
    Abstract: A computer-implemented machine learning model training method and resulting machine learning model. One embodiment of the method may comprise receiving at a computer memory training data; and training on a computer processor a machine learning model on the received training data using a plurality of batch sizes to produce a trained processor. The training may include calculating a plurality of activations during a forward pass of the training and discarding at least some of the calculated plurality of activations after the forward pass of the training.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: February 21, 2023
    Assignee: International Business Machines Corporation
    Inventors: Saurabh Goyal, Anamitra Roy Choudhury, Yogish Sabharwal, Ashish Verma
  • Patent number: 11581878
    Abstract: A level shifter includes a control circuit and a bias circuit. The control circuit receives a bias voltage, a first signal associated with a first voltage domain, and supply voltages associated with a second voltage domain, and outputs a second signal that is associated with the second voltage domain. The bias circuit generates the bias voltage that is indicative of the duty cycle of the second signal, and provides the bias voltage to the control circuit to control the duty cycle of the second signal. The duty cycle of the second signal is controlled such that a difference between a duty cycle of the first signal and an inverse of the duty cycle of the second signal is less than a tolerance limit.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: February 14, 2023
    Assignee: NXP B.V.
    Inventors: Sanjay Kumar Wadhwa, Saurabh Goyal, Divya Tripathi
  • Publication number: 20230015895
    Abstract: Methods, systems, and computer program products for accelerating inference of transformer-based models are provided herein. A computer-implemented method includes obtaining a machine learning model comprising a plurality of transformer blocks, a task, and a natural language dataset; generating a compressed version of the machine learning model based on the task and the natural language dataset, wherein the generating comprises: obtaining at least one set of tokens, wherein each token in the set corresponds to one of the items in the natural language dataset, identifying and removing one or more redundant output activations of different ones of the plurality of transformer blocks for the at least one set of tokens, and adding one or more input activations corresponding to the one or more removed output activations into the machine learning model at subsequent ones of the plurality of the transformer blocks; and outputting the compressed version of the machine learning model to at least one user.
    Type: Application
    Filed: July 12, 2021
    Publication date: January 19, 2023
    Inventors: Saurabh Goyal, Anamitra Roy Choudhury, Saurabh Manish Raje, Venkatesan T. Chakaravarthy, Yogish Sabharwal, Ashish Verma
  • Publication number: 20220358358
    Abstract: Methods, systems, and computer program products for accelerating inference of neural network models via dynamic early exits are provided herein. A computer-implemented method includes determining a plurality of candidate exit points of a neural network model; obtaining a plurality of outputs of the neural network model for data samples in a target dataset, wherein the plurality of outputs comprises early outputs of the neural network model from the plurality of candidate exit points and regular outputs of the neural network model; and a set of one or more exit points from the plurality of candidate exits points that are dependent on the target dataset based at least in part on the plurality of outputs.
    Type: Application
    Filed: May 4, 2021
    Publication date: November 10, 2022
    Inventors: Saurabh Manish Raje, Saurabh Goyal, Anamitra Roy Choudhury, Yogish Sabharwal, Ashish Verma
  • Patent number: 11386036
    Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving, at a circuit, data via a differential input signal, detecting a rising edge in the data received via the differential input signal, and precharging a common mode voltage (Vcm) node of the differential input signal responsive to detecting the rising edge in the data received via the differential input signal, wherein the Vcm node is a floating node.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: July 12, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Win Naing Maung, Saurabh Goyal, Bhupendra Sharma, Huanzhang Huang, Douglas Edward Wente, Suzanne Mary Vining, Mustafa Ulvi Erdogan
  • Patent number: 11378991
    Abstract: A soft-start circuit for a voltage regulator includes a comparator and a delay circuit. The comparator compares an output voltage, that is generated by the voltage regulator, and a reference voltage to generate a comparison signal. Further, the delay circuit receives the reference voltage and a control signal that is outputted based on the comparison signal, and outputs and provides another reference voltage to the voltage regulator. During a start-up of the voltage regulator, the reference voltage outputted by the delay circuit is a delayed version of the reference voltage received by the delay circuit. Thus, the soft-start circuit mitigates an overshoot of the output voltage during the start-up. Further, on completion of the start-up, the reference voltage outputted by the delay circuit is equal to the reference voltage received by the delay circuit.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: July 5, 2022
    Assignee: NXP B.V.
    Inventors: Saurabh Goyal, Sanjay Kumar Wadhwa, Divya Tripathi